bflb,bl61x-flash-clk

Vendor: Bouffalo Lab (Nanjing) Co., Ltd.

Description

The BL61x Flash Clock
Source -> divider -> CLK
Only has settings for Bank 1 (boot flash) at the moment.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

divider

int

Divide source clock by this 3-bits value (1 to 8). Typically 1.

Default value: 1

read-delay

int

Flash Read delay. This is a flash controller setting. This may be necessary to achieve flash clock higher than XCLK.

Legal values: 0, 1, 2, 3

clock-invert

boolean

Invert Clock Signal. This is a flash controller setting. This may be necessary to achieve flash clock higher than XCLK.

rx-clock-invert

boolean

Invert RX Clock Signal. This is a flash controller setting. This may be necessary to achieve flash clock higher than XCLK.

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.