SC-OBC Module A1

Overview

Space Cubics [1] OBC Module A1 (SC-OBC Module A1) is a single board computer for spacecraft, especially for 3U CubeSats. The board is based on Xilinx Artix-7 FPGA and implements ARM Cortex M3 as the main CPU.

It is designed to survive in the severe space environment, extreme temperature, vacuum, and space radiation.

As the name suggests, the board form factor is a module and requires a base I/O board connected at CON1, a board-to-board connector. This modularity allows CubeSat designers the freedom to connect and expand the capability required for their mission.

Hardware

Supported Features

The scobc_a1 board supports the hardware features listed below.

on-chip / on-board
Feature integrated in the SoC / present on the board.
2 / 2
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
scobc_a1
@
/
designstart_fpga_cortex_m3

Type

Location

Description

Compatible

CPU

on-board

ARM Cortex-M3 CPU1

arm,cortex-m3

Interrupt controller

on-chip

ARMv7-M NVIC (Nested Vectored Interrupt Controller)1

arm,v7m-nvic

Miscellaneous

on-board

Space Cubics HRMEM (High-reliability Memory)1

sc,hrmem

on-board

SC-OBC Module A1 System Register1

sc,sysreg

on-board

SC-OBC Module A1 System Monitor1

sc,sysmon

MMU / MPU

on-board

ARMv7-M Memory Protection Unit (MPU)1

arm,armv7m-mpu

Serial controller

on-board

Xilinx UART Lite IP1

xlnx,xps-uartlite-1.00.a

Timer

on-chip

ARMv7-M System Tick1

arm,armv7m-systick

Other hardware features are not currently supported by the port.

System Clock

The board has two 24 MHz external oscillators connected to the FPGA for redundancy. The FPGA will select an active oscillator as CPU system clock. The selected clock signal is then used by the CMT in the FPGA, and drives the CPU at 48 MHz by default.

Serial Port

The default configuration contains one SC UART IP, which is register compatible with Xilinx UART Lite for basic TX and RX. This UART is configured as the default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx, respectively.

Programming and Debugging

The scobc_a1 board supports the runners and associated west commands listed below.

flash debug rtt attach debugserver
openocd ✅ (default) ✅ (default) ✅ ✅ ✅

Flashing

Here is an example for building and flashing the `hello_world` application for the board:

Here is an example for building and flashing the Hello World application for the default design:

# From the root of the zephyr repository
west build -b scobc_a1 samples/hello_world
west flash

After flashing, you should see message similar to the following in the terminal:

*** Booting Zephyr OS build v4.1.0-4619-gd571a59b0a43 ***
Hello World! scobc_a1/designstart_fpga_cortex_m3

Note, however, that the application was not persisted in flash memory by the above steps. It was merely written to internal RAM in the FPGA.

Debugging

Here is an example for the Hello World application.

# From the root of the zephyr repository
west build -b scobc_a1 samples/hello_world
west debug

Step through the application in your debugger, and you should see a message similar to the following in the terminal:

*** Booting Zephyr OS build v4.1.0-4619-gd571a59b0a43 ***
Hello World! scobc_a1/designstart_fpga_cortex_m3

References