ROCK 5B+

Overview

The Radxa ROCK 5B+ is a single-board computer based on the Rockchip RK3588. The SoC combines four Cortex-A76 and four Cortex-A55 CPU cores. The board is available with up to 32 GB of LPDDR5 memory and provides eMMC, microSD, PCIe, USB, Ethernet, and a 40-pin expansion header.

The SMP variant supports all four Cortex-A55 and four Cortex-A76 cores.

Supported Features

The rock_5b_plus board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`rock_5b_plus/rk3588` target

On-target memory for this board target: 128 MiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A55 CPU4	`arm,cortex-a55`
CPU	on-chip	ARM Cortex-A76 CPU4	`arm,cortex-a76`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 0.21	`arm,psci-0.2`
Serial controller	on-chip	ns16550 UART1 1	`ns16550`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`

`rock_5b_plus/rk3588/smp` target

On-target memory for this board target: 128 MiB of RAM, N/A of Flash.

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A55 CPU4	`arm,cortex-a55`
CPU	on-chip	ARM Cortex-A76 CPU4	`arm,cortex-a76`
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	`arm,gic-v3`
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 0.21	`arm,psci-0.2`
Serial controller	on-chip	ns16550 UART1 1	`ns16550`
SRAM	on-board	Generic on-chip SRAM1	`mmio-sram`
Timer	on-chip	per-core ARM architected timer1	`arm,armv8-timer`

The onboard Ethernet interface is not currently supported by Zephyr.

Serial Port

Zephyr uses UART2 as the serial console at 1.5 Mbit/s.

Programming and Debugging

The rock_5b_plus board supports the runners and associated west commands listed below.

	flash	debug

Applications are built with the standard configuration, for example:

# From the root of the zephyr repository
west build -b rock_5b_plus samples/hello_world

To run Zephyr on all eight CPU cores, build the SMP variant:

# From the root of the zephyr repository
west build -b rock_5b_plus//smp samples/synchronization

Create a legacy U-Boot image whose payload loads and runs at 0x10000000:

mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 \
  -d build/zephyr/zephyr.bin build/zephyr/zephyr.img

The Radxa U-Boot AArch64 Linux boot path requires a devicetree. Obtain rk3588-rock-5b-plus.dtb from the Radxa Linux distribution and copy it and zephyr.img to a FAT partition accessible from U-Boot.

Check the temporary kernel and devicetree load addresses provided by U-Boot:

printenv kernel_addr_r fdt_addr_r

Load each file at its corresponding address, then pass the devicetree address to bootm. Adjust the MMC device and partition numbers for the selected boot media:

fatload mmc 1:1 ${kernel_addr_r} zephyr.img
fatload mmc 1:1 ${fdt_addr_r} rk3588-rock-5b-plus.dtb
bootm ${kernel_addr_r} - ${fdt_addr_r}

The legacy image header instructs U-Boot to move the Zephyr payload from kernel_addr_r to 0x10000000 before jumping to the entry point. Keeping the temporary image, devicetree, and Zephyr runtime regions separate avoids overwriting any of them during the handoff.

References

More information is available from the Radxa ROCK 5B+ documentation.