PineCone BL602 Evaluation Board

Overview

The Pine64 PineCone BL602 Evaluation Board is a low-cost development board built around the Bouffalo Lab BL602 Wi-Fi + BLE chipset. The BL60x series has 276KB of RAM, and supports 2.4GHz Wi-Fi 802.11 b/g/n and BLE 5.0.

The PineCone is populated with the BL602C20 package, which provides 2MB SiP flash memory.

Hardware

PineCone provides the following hardware components:

BL602C20 SoC
2 LEDs:
- RGB LED on GPIOs 17, 14 and 11
- Power LED
Reset Button (RST)
CH340N USB-to-UART bridge

For more information about the Bouffalo Lab BL60x MCU and the PineCone board:

Supported Features

The pinecone board supports the hardware features listed below.

on-chip / on-board: Feature integrated in the SoC / present on the board.
2 / 2: Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.
vnd,foo: Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

`pinecone/bl602c20q2i` target

On-target memory for this board target: 216 KiB of RAM, 2 MiB of Flash.

Type	Location	Description	Compatible
CPU	on-chip	SiFive E24 Standard Core CPU1	`sifive,e24`
ADC	on-chip	Bouffalolab ADC1	`bflb,adc`
Bluetooth	on-chip	Bluetooth HCI for Bouffalo Lab on-chip BLE controllers1	`bflb,bt-hci`
Cache	on-chip	Bouffalo Lab L1C cache control1	`bflb,l1c`
Clock control	on-chip	Generic fixed-rate clock provider3 1	`fixed-clock`
	on-chip	Bouffalolab F32K clock1	`bflb,f32k`
	on-chip	Bouffalolab PLL settings1	`bflb,pll`
	on-chip	Bouffalolab Root Clock Represents both FCLK and HCLK depending on their presence, which should be kept the same1	`bflb,root-clk`
	on-chip	The BCLK clock, or peripheral clock Source -> / divider -> This Clock1	`bflb,bclk`
	on-chip	BFLB Flash Clock Source -> divider -> CLK Only has settings for Bank 1 on BL61x (boot flash) at the moment1	`bflb,flash-clk`
	on-chip	Bouffalolab BL60x Clock Controller1	`bflb,bl60x-clock-controller`
Counter	on-chip	Bouffalo Lab General Purpose Timer Block1	`bflb,timer`
	on-chip	Bouffalo Lab Timer Channel (Counter)2	`bflb,timer-channel`
	on-chip	Bouffalo Lab RTC Counter (HBN-based)1	`bflb,rtc`
Cryptographic accelerator	on-chip	Bouffalo Lab SEC Engine TRNG (True Random Number Generator)1	`bflb,sec-eng-trng`
	on-chip	Bouffalo Lab SEC Engine SHA hardware accelerator1	`bflb,sec-eng-sha`
	on-chip	Bouffalo Lab SEC Engine AES hardware accelerator1	`bflb,sec-eng-aes`
DMA	on-chip	Bouffalo Lab DMA1	`bflb,dma`
GPIO & Headers	on-chip	Bouffalo Lab BL60x and BL70x GPIO node1	`bflb,bl60x_70x-gpio`
I2C	on-chip	Bouffalolab I2C interface1	`bflb,i2c`
Input	on-chip	Bouffalolab Infrared Receiver Peripheral Wire the output of a diode like VS1838B to the specified GPIO pin1	`bflb,irx`
Interrupt controller	on-chip	RISC-V CPU interrupt controller1	`riscv,cpu-intc`
Interrupt controller	on-chip	RISC-V Core Local Interrupt Controller CLIC Pre-Standard v0.91	`sifive,clic-draft`
LED	on-board	Group of GPIO-controlled LEDs1	`gpio-leds`
LED	on-board	Group of PWM-controlled LEDs1	`pwm-leds`
Memory controller	on-chip	Serial Flash controller1	`bflb,sf-controller`
Memory controller	on-chip	Serial Flash Controller Bank1	`bflb,sf-bank`
MTD	on-board	Bouffalolab Serial Flash controller Flash1	`bflb,sf-flash`
OTP memory	on-chip	BouffaloLab Efuse1	`bflb,efuse`
Pin control	on-chip	Bouffalo Lab Pinctrl node1	`bflb,pinctrl`
Power management	on-chip	Bouffalolab Power Controller1	`bflb,power-controller`
PWM	on-chip	Bouffalolab PWM 11	`bflb,pwm-1`
Regulator	on-chip	Bouffalolab HBN SoC (CPU, Memory, etc) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,soc-regulator`
	on-chip	Bouffalolab HBN RT (RTC) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,rt-regulator`
	on-chip	Bouffalolab HBN AON (Always ON section) voltage regulator It is a LDO with a canonical voltage of 1.10v It has two modes, but they are only switched between when going into sleep mode and do not share settings areas1	`bflb,aon-regulator`
Sensors	on-chip	Bouffalo Lab internal die temperature sensor (TSEN)1	`bflb,tsen`
Serial controller	on-chip	Bouffalo Lab UART1 1	`bflb,uart`
SPI	on-chip	Bouffalolab SPI1	`bflb,spi`
SRAM	on-chip	Generic on-chip SRAM1 1	`mmio-sram`
Timer	on-chip	RISC-V Machine Timer1	`riscv,machine-timer`
Watchdog	on-chip	Bouffalo Lab Watchdog Timer1	`bflb,wdt`

System Clock

The PineCone board is configured to run at max speed (192 MHz).

Serial Port

The pinecone board uses UART0 as its default serial port (GPIO16 as TX and GPIO7 as RX). It is connected to the on-board CH340 USB-to-UART converter and is used for both programming and console output.

Programming and Debugging

Samples

Build the Zephyr kernel and the Hello World sample application:

# From the root of the zephyr repository
west build -b pinecone samples/hello_world
west flash

To flash, move the boot jumper to the position closest to the board edge (H), press and release RST to enter the boot ROM, then run west flash.
Run your favorite terminal program to listen for output. Under Linux the terminal should be /dev/ttyUSB0. For example:
```
$ screen /dev/ttyUSB0 115200
```
Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Move the boot jumper back and press and release RST.
```
*** Booting Zephyr OS build v4.4.0 ***
Hello World! pinecone/bl602c20q2i
```

Congratulations, you have pinecone configured and running Zephyr.