ET171 Development Board
Overview
The et171 development board is used for development and verification, and can be used for application development through interfaces such as UART, GPIO, SPI, and I2C.
Hardware
The platform provides following hardware components:
32-bit RISC-V CPU
384KB embedded SDRAM
UART
I2C
SPI
GPIO
PWM
DMA
USB
Supported Features
The egis_et171 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
egis_et171/et171 target
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-chip |
Andes Technology RISC-V core from the AndesCore v5 series1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Counter |
on-chip |
This is a representation of the Andes Technology atcpit100 PIT node1 |
|
DMA |
on-chip |
Andes DMA controller channel: a phandle to the DMA controller plus the following four integer cells:1 |
|
GPIO & Headers |
on-chip |
Andes Technology ATCGPIO100 GPIO Controller1 |
|
I2C |
on-chip |
AndesTech ATCIIC100 I2C1 |
|
Interrupt controller |
on-chip |
RISC-V CPU interrupt controller1 |
|
on-chip |
SiFive RISCV-V platform-local interrupt controller2 |
||
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MTD |
on-board |
Flash node1 |
|
Serial controller |
on-chip |
ns16550 UART1 |
|
SRAM |
on-chip |
Generic on-chip SRAM1 |
|
System controller |
on-chip |
System Controller Registers R/W1 |
|
Timer |
on-chip |
RISC-V Machine Timer1 |
|
Watchdog |
on-chip |
Andes Watchdog driver1 |
Connections and IOs
The et171 platform has 1 GPIO controller. It providing 17 bits of IO. It is responsible for pin input/output, pull-up, etc.
The et171 platform has 3 SPI controllers, 2 of which can additionally support QSPI and XIP mode.
The et171 platform has one USB 2.0 controller that supports up to USB 2.0 high-speed mode.
Except USB DP/DM, all et171 peripheral I/O devices are mapped to 31 I/O pins through the multiplexer controller.
System Clock
The et171 platform has a multi-stage frequency divider with a maximum speed of 200 MHz.
Programming and debugging
The egis_et171 board supports the runners and associated west commands listed below.
| flash | debug | |
|---|---|---|
| misc-flasher | ✅ (default) |
The et171 is compatible with Andes ae350, so you can use Andes ICE for debugging. For debugging zephyr applications or upload them into a RAM, you will need to connect ICE from host computer to et171 board and execute the ICE management software, ICEman, on this host computer.
Connecting Andes ICE (AICE)
AICE is used for debugging and uploading RAM code to the board.
Building
You can build applications in the usual way. Here is an example for the Hello World application.
# From the root of the zephyr repository
west build -b egis_et171 samples/hello_world
Flashing
Since this is a B2B prototype, there is no publicly available flashing tool. If you have any development needs, please contact the contact window of Egis Technology Inc. .
If you has a debugger (AICE-MICRO [1]) with ICEman (Andes Development Kit [2])
, set the CONFIG_XIP=n to enable running the program in RAM mode via
the ICE debugger.
At first, you should run ICEman before load program.
# Enable execute file permission of ICEman
$ chmod a+x ./ICEman
# Running the ICEman server
$ sudo ./ICEman -Z v5
# When your ICEman server is running
# You can load the program into RAM and execute it via gdb
$ riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf
(gdb) target remote :1111
(gdb) monitor reset halt
(gdb) load
(gdb) quit