MPS3 FPGA/Corstone FVP
Overview
The mps3 board configuration is used by Zephyr applications that run on the MPS3 board. It provides support for multiple Arm FPGA images and simulation models:
AN536 supports Arm Cortex-R52 CPU
AN547 and AN552 support Arm Cortex-M55 CPU
AN555 support Arm Cortex-M85 CPU
Corstone-300 and Corstone-310 FVPs are supported for selected Cortex-M configurations
Depending on the selected board target, it provides support for the following devices:
Nested Vectored Interrupt Controller (NVIC)
System Tick System Clock (SYSTICK)
Generic Interrupt Controller v3 (GICv3)
Arm architectural timer
Cortex-M System Design Kit GPIO
Cortex-M System Design Kit UART
Ethos-U55 NPU
Corstone-300 FVP/Corstone-310 FVP (Fixed Virtual Platforms) are complete simulations of Arm systems, including processor, memory and peripherals. They are available free of charge for Linux and Windows systems. The FVPs have been selected for simulation since they provide access to the Ethos-U55 NPU, which is unavailable in QEMU or other simulation platforms.
The AN536 Cortex-R52x2 subsystem is supported with QEMU using the mps3-an536 machine.
Zephyr board options
The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
BOARD |
Description |
|---|---|
|
For building Secure (or Secure-only) firmware |
|
For building Non-Secure firmware |
- FPGA Usage:
Follow Programming and Debugging for build and flash instructions.
- FVP Usage:
FVP is not supported for this variant.
- QEMU Usage:
To run with QEMU instead of the default FVP, override the emulator selection at build time via:
$ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run
The MPS3+ AN552 is an SoC with Cortex-M55 architecture. Zephyr provides support for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
BOARD |
Description |
|---|---|
|
For building Secure (or Secure-only) firmware |
|
For building Non-Secure firmware |
- FPGA Usage:
Follow Programming and Debugging for build and flash instructions.
- FVP Usage:
FVP not supported for this variant.
- QEMU Usage:
QEMU not supported for this variant of board.
The MPS3+ FVP is an SoC with Cortex-M55 architecture. Zephyr provides support for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
BOARD |
Description |
|---|---|
|
For building Secure (or Secure-only) firmware |
|
For building Non-Secure firmware |
- FPGA Usage:
N/A.
- FVP Usage:
To run with the FVP, first set environment variable
ARMFVP_BIN_PATHbefore using it. Then you can run it withwest build -t run.
export ARMFVP_BIN_PATH=/path/to/fvp/directory west build -b {BOARD qualifier from table above} samples/hello_world -t run
To run the Fixed Virtual Platform simulation tool you must download “FVP model for the Corstone-300 MPS3” from Arm and install it on your host PC. This board has been tested with version 11.24.13 (Jan 4 2024).
- QEMU Usage:
N/A.
The MPS3+ AN555 is an SoC with Cortex-M85 architecture. Zephyr provides support for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
BOARD |
Description |
|---|---|
|
For building Secure (or Secure-only) firmware |
|
For building Non-Secure firmware |
- FPGA Usage:
Follow Programming and Debugging for build and flash instructions.
- FVP Usage:
FVP not supported for this variant.
- QEMU Usage:
QEMU not supported for this variant of board.
The MPS3+ FVP is an SoC with Cortex-M85 architecture. Zephyr provides support for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
BOARD |
Description |
|---|---|
|
For building Secure (or Secure-only) firmware |
|
For building Non-Secure firmware |
- FPGA Usage:
N/A.
- FVP Usage:
To run with the FVP, first set environment variable
ARMFVP_BIN_PATHbefore using it. Then you can run it withwest build -t run.
export ARMFVP_BIN_PATH=/path/to/fvp/directory west build -b {BOARD qualifier from table above} samples/hello_world -t run
To run the Fixed Virtual Platform simulation tool you must download “FVP model for the Corstone-310 MPS3” from Arm and install it on your host PC. This board has been tested with version 11.24.13 (Jan 4 2024).
- QEMU Usage:
N/A.
The MPS3 AN536 is an example Cortex-R52x2 subsystem. Zephyr currently supports building for CPU0.
The BOARD option is summarized below:
BOARD |
Description |
|---|---|
|
For building firmware for R52 CPU0 |
- FPGA Usage:
N/A.
- FVP Usage:
N/A.
- QEMU Usage:
To run with QEMU:
west build -b mps3/an536/cpu0 samples/hello_world -t run
Note
Board qualifier must include the board name as mentioned above.
mps3/corstone300, mps3/corstone310 or mps3/an536 without
the full board qualifier is not valid.
Hardware
ARM MPS3 provides the following hardware components:
CPU
AN547 and AN552 support Arm Cortex-M55 CPU and Soft Macro Model (SMM) implementation of SSE-300 subsystem
AN555 support Arm Cortex-M85 CPU and Soft Macro Model (SMM) implementation of SSE-310 subsystem
AN536 supports Arm Cortex-R52 CPU and an example Cortex-R52x2 subsystem
Memory
8MB BRAM
4GB DDR4 SODIMM (by default, upgradeable to 8GB)
16GB eMMC
8MB QSPI Flash
Debug
P‐JTAG, F-JTAG, SWD, 4-bit trace, 16-bit trace
Four serial ports over USB
Interface
AHB GPIO
UART
SPI
I2C
I2S
Color LCD serial interface
Ethernet
VGA
On-board Peripherals
Color LCD
10 LEDs
8 Switches
2 user push buttons
Supported Features
The mps3 board supports the hardware features listed below.
- on-chip / on-board
- Feature integrated in the SoC / present on the board.
- 2 / 2
-
Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files. -
vnd,foo -
Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.
mps3/an536/cpu0 target
On-target memory for this board target: 512 KiB of RAM, N/A of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
||
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Interrupt controller |
on-board |
ARM Generic Interrupt Controller v31 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
SRAM |
on-board |
||
Timer |
on-board |
per-core ARM architected timer1 |
|
Watchdog |
on-board |
ARM CMSDK watchdog1 |
mps3/corstone300/an547 target
On-target memory for this board target: 512 KiB of RAM, 512 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
ARM Cortex-M55 CPU1 |
|
ARM architecture |
on-board |
The Arm Ethos-U is a micro NPU that enables neural networks to be hardware accelerated on embedded devices1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Ethernet |
on-board |
SMSC (now Microchip) LAN9220 Ethernet controller1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
on-board |
ARM MMIO32 GPIO3 |
||
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MMU / MPU |
on-board |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
mps3/corstone300/an552 target
On-target memory for this board target: 512 KiB of RAM, 512 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
ARM Cortex-M55 CPU1 |
|
ARM architecture |
on-board |
The Arm Ethos-U is a micro NPU that enables neural networks to be hardware accelerated on embedded devices1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Ethernet |
on-board |
SMSC (now Microchip) LAN9220 Ethernet controller1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
on-board |
ARM MMIO32 GPIO3 |
||
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MMU / MPU |
on-board |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
mps3/corstone300/fvp target
On-target memory for this board target: 512 KiB of RAM, 512 KiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
ARM Cortex-M55 CPU1 |
|
ARM architecture |
on-board |
The Arm Ethos-U is a micro NPU that enables neural networks to be hardware accelerated on embedded devices1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Ethernet |
on-board |
SMSC (now Microchip) LAN9220 Ethernet controller1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
on-board |
ARM MMIO32 GPIO3 |
||
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MMU / MPU |
on-board |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
mps3/corstone310/an555 target
On-target memory for this board target: 2 MiB of RAM, 4 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
ARM Cortex-M85 CPU1 |
|
ARM architecture |
on-board |
The Arm Ethos-U is a micro NPU that enables neural networks to be hardware accelerated on embedded devices1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Ethernet |
on-board |
SMSC (now Microchip) LAN9220 Ethernet controller1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
on-board |
ARM MMIO32 GPIO3 |
||
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MMU / MPU |
on-board |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
mps3/corstone310/fvp target
On-target memory for this board target: 2 MiB of RAM, 4 MiB of Flash.
Type |
Location |
Description |
Compatible |
|---|---|---|---|
CPU |
on-board |
ARM Cortex-M85 CPU1 |
|
ARM architecture |
on-board |
The Arm Ethos-U is a micro NPU that enables neural networks to be hardware accelerated on embedded devices1 |
|
Clock control |
on-board |
Generic fixed-rate clock provider1 |
|
Ethernet |
on-board |
SMSC (now Microchip) LAN9220 Ethernet controller1 |
|
GPIO & Headers |
on-board |
ARM CMSDK GPIO4 |
|
on-board |
ARM MMIO32 GPIO3 |
||
I2C |
on-board |
ARM SBCon two-wire serial bus interface5 |
|
Input |
on-board |
Group of GPIO-bound input keys1 |
|
Interrupt controller |
on-chip |
ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)1 |
|
LED |
on-board |
Group of GPIO-controlled LEDs1 |
|
MMU / MPU |
on-board |
ARMv8.1-M MPU (Memory Protection Unit)1 |
|
Pin control |
on-board |
Arm MPS3 Pin Controller1 |
|
Serial controller |
on-board |
||
SPI |
on-board |
ARM PL022 SPI3 |
|
Timer |
on-chip |
ARMv8.1-M System Tick1 |
Serial Port
The MPS3 has six UARTs. The Zephyr console output by default, uses UART0, which is exposed over the Debug USB interface (J8).
Serial port 0 on the Debug USB interface is the MCC board control console.
Serial port 1 on the Debug USB interface is connected to UART 0.
Serial port 2 on the Debug USB interface is connected to UART 1.
Serial port 3 on the Debug USB interface is connected to UART 2.
For AN536, the Cortex-R52x2 subsystem provides LLPP UART0 and LLPP UART1
as CPU-private UARTs, and additional shared CMSDK UARTs. The
mps3/an536/cpu0 target uses LLPP UART0 as the Zephyr console.
Programming and Debugging
Flashing
MPS3 provides:
A USB connection to the host computer, which exposes Mass Storage and CMSIS-DAP, and serial ports.
Building an application with AN547
You can build applications in the usual way. Here is an example for the Hello World application with AN547.
# From the root of the zephyr repository
west build -b mps3/corstone300/an547 samples/hello_world
Open a serial terminal (minicom, putty, etc.) with the following settings:
Speed: 115200
Data: 8 bits
Parity: None
Stop bits: 1
Reset the board, and you should see the following message on the corresponding serial port:
Hello World! mps3
Uploading an application to MPS3 AN547
Applications can be in elf, hex or bin format. The binaries are flashed when the board boots up, using files stored on the on-board Micro SD card. The Motherboard Configuration Controller (MCC) is responsible for loading the FPGA image and binaries.
Connect the MPS3 to your host computer using the USB port. You should see a
USB connection exposing a Mass Storage (V2M-MPS3 by default).
The update requires 3 steps:
Copy application files to
<MPS3 device name>/SOFTWARE/.Open
<MPS3 device name>/MB/HBI0309C/AN547/images.txt.Update the
images.txtfile as follows:
TITLE: Versatile Express Images Configuration File
[IMAGES]
TOTALIMAGES: 1 ;Number of Images (Max: 32)
IMAGE0ADDRESS: 0x01000000 ;Please select the required executable program
IMAGE0FILE: \SOFTWARE\zephyr.elf
Reset the board, and you should see the following message on the corresponding serial port:
Hello World! mps3
Building and running an application with AN536
You can build applications in the usual way. Here is an example for the Hello World application with AN536.
# From the root of the zephyr repository
west build -b mps3/an536/cpu0 samples/hello_world
To run the application with QEMU:
# From the root of the zephyr repository
west build -b mps3/an536/cpu0 samples/hello_world
west build -t run
You should see the following message:
Hello World! mps3/an536/cpu0
- For more details refer to: