tisci.h

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/*
 * Copyright (c) 2025, Texas Instruments
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef INCLUDE_ZEPHYR_DRIVERS_TISCI_H_
#define INCLUDE_ZEPHYR_DRIVERS_TISCI_H_
 
#include <zephyr/device.h>
 
#define MAILBOX_MBOX_SIZE 60

struct tisci_version_info {
        uint8_t abi_major;
        uint8_t abi_minor;
        uint16_t firmware_revision;
        char firmware_description[32];
};
struct tisci_version_info {…};

struct tisci_msg_fwl_region {
        uint16_t fwl_id;
        uint16_t region;
        uint32_t n_permission_regs;
        uint32_t control;
        uint32_t permissions[3];
        uint64_t start_address;
        uint64_t end_address;
};
struct tisci_msg_fwl_region {…};

struct tisci_msg_fwl_owner {
        uint16_t fwl_id;
        uint16_t region;
        uint8_t owner_index;
        uint8_t owner_privid;
        uint16_t owner_permission_bits;
};
struct tisci_msg_fwl_owner {…};

struct tisci_msg_rm_udmap_tx_ch_cfg {
        uint32_t valid_params;
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID    BIT(9)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID  BIT(10)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID    BIT(11)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID  BIT(12)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID        BIT(13)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID        BIT(15)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
        uint16_t nav_id;
        uint16_t index;
        uint8_t tx_pause_on_err;
        uint8_t tx_filt_einfo;
        uint8_t tx_filt_pswords;
        uint8_t tx_atype;
        uint8_t tx_chan_type;
        uint8_t tx_supr_tdpkt;
        uint16_t tx_fetch_size;
        uint8_t tx_credit_count;
        uint16_t txcq_qnum;
        uint8_t tx_priority;
        uint8_t tx_qos;
        uint8_t tx_orderid;
        uint16_t fdepth;
        uint8_t tx_sched_priority;
        uint8_t tx_burst_size;
        uint8_t tx_tdtype;
        uint8_t extended_ch_type;
};
struct tisci_msg_rm_udmap_tx_ch_cfg {…};

struct tisci_msg_rm_udmap_rx_ch_cfg {
        uint32_t valid_params;
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID   BIT(10)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
#define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID  BIT(12)
        uint16_t nav_id;
        uint16_t index;
        uint16_t rx_fetch_size;
        uint16_t rxcq_qnum;
        uint8_t rx_priority;
        uint8_t rx_qos;
        uint8_t rx_orderid;
        uint8_t rx_sched_priority;
        uint16_t flowid_start;
        uint16_t flowid_cnt;
        uint8_t rx_pause_on_err;
        uint8_t rx_atype;
        uint8_t rx_chan_type;
        uint8_t rx_ignore_short;
        uint8_t rx_ignore_long;
        uint8_t rx_burst_size;
};
struct tisci_msg_rm_udmap_rx_ch_cfg {…};
 
#define TISCI_MSG_VALUE_RM_DST_ID_VALID                (1u << 0u)
#define TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID          (1u << 1u)
#define TISCI_MSG_VALUE_RM_IA_ID_VALID                 (1u << 2u)
#define TISCI_MSG_VALUE_RM_VINT_VALID                  (1u << 3u)
#define TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID          (1u << 4u)
#define TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID (1u << 5u)

struct tisci_irq_set_req {
        uint32_t valid_params;
        uint16_t src_id;
        uint16_t src_index;
        uint16_t dst_id;
        uint16_t dst_host_irq;
        uint16_t ia_id;
        uint16_t vint;
        uint16_t global_event;
        uint8_t vint_status_bit_index;
        uint8_t secondary_host;
};
struct tisci_irq_set_req {…};

 
struct tisci_irq_release_req {
        uint32_t valid_params;
        uint16_t src_id;
        uint16_t src_index;
        uint16_t dst_id;
        uint16_t dst_host_irq;
        uint16_t ia_id;
        uint16_t vint;
        uint16_t global_event;
        uint8_t vint_status_bit_index;
        uint8_t secondary_host;
};
struct tisci_irq_release_req {…};
 
/* Version/Revision Functions */

int tisci_cmd_get_revision(const struct device *dev, struct tisci_version_info *ver);
 
/* Clock Management Functions */

int tisci_cmd_get_clock_state(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                              uint8_t *programmed_state, uint8_t *current_state);

int tisci_set_clock_state(const struct device *dev, uint32_t dev_id, uint8_t clk_id, uint32_t flags,
                          uint8_t state);

int tisci_cmd_clk_is_on(const struct device *dev, uint32_t dev_id, uint8_t clk_id, bool *req_state,
                        bool *curr_state);

int tisci_cmd_clk_is_off(const struct device *dev, uint32_t dev_id, uint8_t clk_id, bool *req_state,
                         bool *curr_state);

int tisci_cmd_clk_is_auto(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                          bool *req_state);

int tisci_cmd_clk_get_freq(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                           uint64_t *freq);

int tisci_cmd_clk_set_freq(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                           uint64_t min_freq, uint64_t target_freq, uint64_t max_freq);

int tisci_cmd_clk_get_match_freq(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                                 uint64_t min_freq, uint64_t target_freq, uint64_t max_freq,
                                 uint64_t *match_freq);

int tisci_cmd_clk_set_parent(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                             uint8_t parent_id);

int tisci_cmd_clk_get_parent(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                             uint8_t *parent_id);

int tisci_cmd_clk_get_num_parents(const struct device *dev, uint32_t dev_id, uint8_t clk_id,
                                  uint8_t *num_parents);

int tisci_cmd_get_clock(const struct device *dev, uint32_t dev_id, uint8_t clk_id, bool needs_ssc,
                        bool can_change_freq, bool enable_input_term);

int tisci_cmd_idle_clock(const struct device *dev, uint32_t dev_id, uint8_t clk_id);

int tisci_cmd_put_clock(const struct device *dev, uint32_t dev_id, uint8_t clk_id);
 
/* Device Management Functions */

int tisci_set_device_state(const struct device *dev, uint32_t dev_id, uint32_t flags,
                           uint8_t state);

int tisci_set_device_state_no_wait(const struct device *dev, uint32_t dev_id, uint32_t flags,
                                   uint8_t state);

int tisci_get_device_state(const struct device *dev, uint32_t dev_id, uint32_t *clcnt,
                           uint32_t *resets, uint8_t *p_state, uint8_t *c_state);

int tisci_cmd_get_device(const struct device *dev, uint32_t dev_id);
int tisci_cmd_get_device_exclusive(const struct device *dev, uint32_t dev_id);

int tisci_cmd_idle_device(const struct device *dev, uint32_t dev_id);
int tisci_cmd_idle_device_exclusive(const struct device *dev, uint32_t dev_id);

int tisci_cmd_put_device(const struct device *dev, uint32_t dev_id);

int tisci_cmd_dev_is_valid(const struct device *dev, uint32_t dev_id);

int tisci_cmd_dev_get_clcnt(const struct device *dev, uint32_t dev_id, uint32_t *count);

int tisci_cmd_dev_is_idle(const struct device *dev, uint32_t dev_id, bool *r_state);

int tisci_cmd_dev_is_stop(const struct device *dev, uint32_t dev_id, bool *r_state,
                          bool *curr_state);

int tisci_cmd_dev_is_on(const struct device *dev, uint32_t dev_id, bool *r_state, bool *curr_state);

int tisci_cmd_dev_is_trans(const struct device *dev, uint32_t dev_id, bool *curr_state);

int tisci_cmd_set_device_resets(const struct device *dev, uint32_t dev_id, uint32_t reset_state);

int tisci_cmd_get_device_resets(const struct device *dev, uint32_t dev_id, uint32_t *reset_state);
 
/* Resource Management Functions */

int tisci_get_resource_range(const struct device *dev, uint32_t dev_id, uint8_t subtype,
                             uint8_t s_host, uint16_t *range_start, uint16_t *range_num);

int tisci_cmd_get_resource_range(const struct device *dev, uint32_t dev_id, uint8_t subtype,
                                 uint16_t *range_start, uint16_t *range_num);

int tisci_cmd_get_resource_range_from_shost(const struct device *dev, uint32_t dev_id,
                                            uint8_t subtype, uint8_t s_host, uint16_t *range_start,
                                            uint16_t *range_num);
 
/* Processor Management Functions */

int tisci_cmd_proc_request(const struct device *dev, uint8_t proc_id);

int tisci_cmd_proc_release(const struct device *dev, uint8_t proc_id);

int tisci_cmd_proc_handover(const struct device *dev, uint8_t proc_id, uint8_t host_id);

int tisci_cmd_set_proc_boot_cfg(const struct device *dev, uint8_t proc_id, uint64_t bootvector,
                                uint32_t config_flags_set, uint32_t config_flags_clear);

int tisci_cmd_set_proc_boot_ctrl(const struct device *dev, uint8_t proc_id,
                                 uint32_t control_flags_set, uint32_t control_flags_clear);

int tisci_cmd_proc_auth_boot_image(const struct device *dev, uint64_t *image_addr,
                                   uint32_t *image_size);

int tisci_cmd_get_proc_boot_status(const struct device *dev, uint8_t proc_id, uint64_t *bv,
                                   uint32_t *cfg_flags, uint32_t *ctrl_flags, uint32_t *sts_flags);

int tisci_proc_wait_boot_status_no_wait(const struct device *dev, uint8_t proc_id,
                                        uint8_t num_wait_iterations, uint8_t num_match_iterations,
                                        uint8_t delay_per_iteration_us,
                                        uint8_t delay_before_iterations_us,
                                        uint32_t status_flags_1_set_all_wait,
                                        uint32_t status_flags_1_set_any_wait,
                                        uint32_t status_flags_1_clr_all_wait,
                                        uint32_t status_flags_1_clr_any_wait);

int tisci_cmd_proc_shutdown_no_wait(const struct device *dev, uint8_t proc_id);
 
/* Board Configuration Functions */

int cmd_set_board_config_using_msg(const struct device *dev, uint16_t msg_type, uint64_t addr,
                                   uint32_t size);
 
/* Ring Configuration Function */

int tisci_cmd_ring_config(const struct device *dev, uint32_t valid_params, uint16_t nav_id,
                          uint16_t index, uint32_t addr_lo, uint32_t addr_hi, uint32_t count,
                          uint8_t mode, uint8_t size, uint8_t order_id);
 
/* System Control Functions */

int tisci_cmd_sys_reset(const struct device *dev);
 
/* Memory Management Functions */

int tisci_cmd_query_msmc(const struct device *dev, uint64_t *msmc_start, uint64_t *msmc_end);
 
/* Firewall Management Functions */

int tisci_cmd_set_fwl_region(const struct device *dev, const struct tisci_msg_fwl_region *region);
 
/* INCLUDE_ZEPHYR_DRIVERS_TISCI_H_ */
 
/* Firewall Management Functions */
/* ... previous firewall functions ... */

int tisci_cmd_get_fwl_region(const struct device *dev, struct tisci_msg_fwl_region *region);
 
/* INCLUDE_ZEPHYR_DRIVERS_TISCI_H_ */
 
/* Firewall Management Functions */
/* ... previous firewall functions ... */

int tisci_cmd_get_fwl_region(const struct device *dev, struct tisci_msg_fwl_region *region);
 
/* Firewall Management Functions */
/* ... previous firewall functions ... */

int tisci_cmd_get_fwl_region(const struct device *dev, struct tisci_msg_fwl_region *region);
 
/* Firewall Management Functions */
/* ... previous firewall functions ... */

int tisci_cmd_change_fwl_owner(const struct device *dev, struct tisci_msg_fwl_owner *owner);
 
/* UDMAP Management Functions */

int tisci_cmd_rm_udmap_tx_ch_cfg(const struct device *dev,
                                 const struct tisci_msg_rm_udmap_tx_ch_cfg *params);

int tisci_cmd_rm_udmap_rx_ch_cfg(const struct device *dev,
                                 const struct tisci_msg_rm_udmap_rx_ch_cfg *params);
 
/* PSI-L Management Functions */

int tisci_cmd_rm_psil_pair(const struct device *dev, uint32_t nav_id, uint32_t src_thread,
                           uint32_t dst_thread);

int tisci_cmd_rm_psil_unpair(const struct device *dev, uint32_t nav_id, uint32_t src_thread,
                             uint32_t dst_thread);

int tisci_cmd_rm_irq_set(const struct device *dev, struct tisci_irq_set_req *req);

int tisci_cmd_rm_irq_release(const struct device *dev, struct tisci_irq_release_req *req);
#endif