Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
ti-cc32xx-pinctrl.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2021 Nordic Semiconductor ASA
3
* SPDX-License-Identifier: Apache-2.0
4
*/
5
6
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
7
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
8
9
/*
10
* The whole TI CC32XX pin configuration information is encoded in a 32-bit
11
* bitfield organized as follows:
12
*
13
* - 31..22: Reserved
14
* - 21..16: Pin.
15
* - 15..10: Reserved.
16
* - 9: Pull-down flag.
17
* - 8: Pull-up flag.
18
* - 7..5: Drive strength.
19
* - 4: Enable open-drain flag.
20
* - 3..0: Configuration mode
21
*
22
* Note that the lower bits (11..0) map directly to the MEM_GPIO_PAD_CONFIG
23
* register.
24
*/
25
31
#define TI_CC32XX_PIN_MSK 0x3FU
32
#define TI_CC32XX_PIN_POS 16U
33
#define TI_CC32XX_MUX_MSK 0xFU
34
#define TI_CC32XX_MUX_POS 0U
35
44
#define TI_CC32XX_PINMUX(pin, mux) \
45
((((pin)&TI_CC32XX_PIN_MSK) << TI_CC32XX_PIN_POS) | \
46
(((mux)&TI_CC32XX_MUX_MSK) << TI_CC32XX_MUX_POS))
47
53
#define GPIO10_P1 TI_CC32XX_PINMUX(1U, 0U)
54
#define I2C_SCL_P1 TI_CC32XX_PINMUX(1U, 1U)
55
#define GT_PWM06_P1 TI_CC32XX_PINMUX(1U, 3U)
56
#define UART1_TX_P1 TI_CC32XX_PINMUX(1U, 7U)
57
#define SDCARD_CLK_P1 TI_CC32XX_PINMUX(1U, 6U)
58
#define GT_CCP01_P1 TI_CC32XX_PINMUX(1U, 12U)
59
60
#define GPIO11_P2 TI_CC32XX_PINMUX(2U, 0U)
61
#define I2C_SDA_P2 TI_CC32XX_PINMUX(2U, 1U)
62
#define GT_PWM07_P2 TI_CC32XX_PINMUX(2U, 3U)
63
#define PXCLK_P2 TI_CC32XX_PINMUX(2U, 4U)
64
#define SDCARD_CMD_P2 TI_CC32XX_PINMUX(2U, 6U)
65
#define UART1_RX_P2 TI_CC32XX_PINMUX(2U, 7U)
66
#define GT_CCP02_P2 TI_CC32XX_PINMUX(2U, 12U)
67
#define MCAFSX_P2 TI_CC32XX_PINMUX(2U, 13U)
68
69
#define GPIO12_P3 TI_CC32XX_PINMUX(3U, 0U)
70
#define MCACLK_P3 TI_CC32XX_PINMUX(3U, 3U)
71
#define PVS_P3 TI_CC32XX_PINMUX(3U, 4U)
72
#define I2C_SCL_P3 TI_CC32XX_PINMUX(3U, 5U)
73
#define UART0_TX_P3 TI_CC32XX_PINMUX(3U, 7U)
74
#define GT_CCP03_P3 TI_CC32XX_PINMUX(3U, 12U)
75
76
#define GPIO13_P4 TI_CC32XX_PINMUX(4U, 0U)
77
#define I2C_SDA_P4 TI_CC32XX_PINMUX(4U, 5U)
78
#define PHS_P4 TI_CC32XX_PINMUX(4U, 4U)
79
#define UART0_RX_P4 TI_CC32XX_PINMUX(4U, 7U)
80
#define GT_CCP04_P4 TI_CC32XX_PINMUX(4U, 12U)
81
82
#define GPIO14_P5 TI_CC32XX_PINMUX(5U, 0U)
83
#define I2C_SCL_P5 TI_CC32XX_PINMUX(5U, 5U)
84
#define GSPI_CLK_P5 TI_CC32XX_PINMUX(5U, 7U)
85
#define PDATA8_P5 TI_CC32XX_PINMUX(5U, 4U)
86
#define GT_CCP05_P5 TI_CC32XX_PINMUX(5U, 12U)
87
88
#define GPIO15_P6 TI_CC32XX_PINMUX(6U, 0U)
89
#define I2C_SDA_P6 TI_CC32XX_PINMUX(6U, 5U)
90
#define GSPI_MISO_P6 TI_CC32XX_PINMUX(6U, 7U)
91
#define PDATA9_P6 TI_CC32XX_PINMUX(6U, 4U)
92
#define SDCARD_DATA3_P6 TI_CC32XX_PINMUX(6U, 8U)
93
#define GT_CCP06_P6 TI_CC32XX_PINMUX(6U, 13U)
94
95
#define GPIO16_P7 TI_CC32XX_PINMUX(7U, 0U)
96
#define GSPI_MOSI_P7 TI_CC32XX_PINMUX(7U, 7U)
97
#define PDATA10_P7 TI_CC32XX_PINMUX(7U, 4U)
98
#define UART1_TX_P7 TI_CC32XX_PINMUX(7U, 5U)
99
#define SDCARD_CLK_P7 TI_CC32XX_PINMUX(7U, 8U)
100
#define GT_CCP07_P7 TI_CC32XX_PINMUX(7U, 13U)
101
102
#define GPIO17_P8 TI_CC32XX_PINMUX(8U, 0U)
103
#define UART1_RX_P8 TI_CC32XX_PINMUX(8U, 5U)
104
#define GSPI_CS_P8 TI_CC32XX_PINMUX(8U, 7U)
105
#define SDCARD_CMD_P8 TI_CC32XX_PINMUX(8U, 8U)
106
#define PDATA11_P8 TI_CC32XX_PINMUX(8U, 4U)
107
108
#define GPIO22_P15 TI_CC32XX_PINMUX(15U, 0U)
109
#define MCAFSX_P15 TI_CC32XX_PINMUX(15U, 7U)
110
#define GT_CCP04_P15 TI_CC32XX_PINMUX(15U, 5U)
111
112
#define GPIO23_P16 TI_CC32XX_PINMUX(16U, 0U)
113
#define TDI_P16 TI_CC32XX_PINMUX(16U, 1U)
114
#define UART1_TX_P16 TI_CC32XX_PINMUX(16U, 2U)
115
#define I2C_SCL_P16 TI_CC32XX_PINMUX(16U, 9U)
116
117
#define GPIO24_P17 TI_CC32XX_PINMUX(17U, 0U)
118
#define TDO_P17 TI_CC32XX_PINMUX(17U, 1U)
119
#define PWM0_P17 TI_CC32XX_PINMUX(17U, 5U)
120
#define UART1_RX_P17 TI_CC32XX_PINMUX(17U, 2U)
121
#define I2C_SDA_P17 TI_CC32XX_PINMUX(17U, 9U)
122
#define GT_CCP06_P17 TI_CC32XX_PINMUX(17U, 4U)
123
#define MCAFSX_P17 TI_CC32XX_PINMUX(17U, 6U)
124
125
#define GPIO28_P18 TI_CC32XX_PINMUX(18U, 0U)
126
127
#define TCK_P19 TI_CC32XX_PINMUX(19U, 1U)
128
#define GT_PWM03_P19 TI_CC32XX_PINMUX(19U, 8U)
129
130
#define GPIO29_P20 TI_CC32XX_PINMUX(20U, 0U)
131
#define TMS_P20 TI_CC32XX_PINMUX(20U, 1U)
132
133
#define GPIO25_P21 TI_CC32XX_PINMUX(21U, 0U)
134
#define GT_PWM02_P21 TI_CC32XX_PINMUX(21U, 9U)
135
#define MCASFX_P21 TI_CC32XX_PINMUX(21U, 2U)
136
137
#define ANTSEL1_P29 TI_CC32XX_PINMUX(29U, 0U)
138
139
#define ANTSEL2_P30 TI_CC32XX_PINMUX(30U, 0U)
140
141
#define GPIO31_P45 TI_CC32XX_PINMUX(45U, 0U)
142
#define UART0_RX_P45 TI_CC32XX_PINMUX(45U, 9U)
143
#define MCAFSX_P45 TI_CC32XX_PINMUX(45U, 12U)
144
#define UART1_RX_P45 TI_CC32XX_PINMUX(45U, 2U)
145
#define MCAXR0_P45 TI_CC32XX_PINMUX(45U, 6U)
146
#define GSPI_CLK_P45 TI_CC32XX_PINMUX(45U, 7U)
147
148
#define GPIO0_P50 TI_CC32XX_PINMUX(50U, 0U)
149
#define UART0_CTSN_P50 TI_CC32XX_PINMUX(50U, 12U)
150
#define MCAXR1_P50 TI_CC32XX_PINMUX(50U, 6U)
151
#define GT_CCP00_P50 TI_CC32XX_PINMUX(50U, 7U)
152
#define GSPI_CS_P50 TI_CC32XX_PINMUX(50U, 9U)
153
#define UART1_RTS_P50 TI_CC32XX_PINMUX(50U, 10U)
154
#define UART0_RTS_P50 TI_CC32XX_PINMUX(50U, 3U)
155
#define MCAXR0_P50 TI_CC32XX_PINMUX(50U, 4U)
156
157
#define GPIO32_P52 TI_CC32XX_PINMUX(52U, 0U)
158
#define MCACLK_P52 TI_CC32XX_PINMUX(52U, 2U)
159
#define MCAXR0_P52 TI_CC32XX_PINMUX(52U, 4U)
160
#define UART0_RTS_P52 TI_CC32XX_PINMUX(52U, 6U)
161
#define GSPI_MOSI_P52 TI_CC32XX_PINMUX(52U, 8U)
162
163
#define GPIO30_P53 TI_CC32XX_PINMUX(53U, 0U)
164
#define UART0_TX_P53 TI_CC32XX_PINMUX(53U, 9U)
165
#define MCACLK_P53 TI_CC32XX_PINMUX(53U, 2U)
166
#define MCAFSX_P53 TI_CC32XX_PINMUX(53U, 3U)
167
#define GT_CCP05_P53 TI_CC32XX_PINMUX(53U, 4U)
168
#define GSPI_MISO_P53 TI_CC32XX_PINMUX(53U, 7U)
169
170
#define GPIO1_P55 TI_CC32XX_PINMUX(55U, 0U)
171
#define UART0_TX_P55 TI_CC32XX_PINMUX(55U, 3U)
172
#define PCLK_P55 TI_CC32XX_PINMUX(55U, 4U)
173
#define UART1_TX_P55 TI_CC32XX_PINMUX(55U, 6U)
174
#define GT_CCP01_P55 TI_CC32XX_PINMUX(55U, 7U)
175
176
#define GPIO2_P57 TI_CC32XX_PINMUX(57U, 0U)
177
#define UART0_RX_P57 TI_CC32XX_PINMUX(57U, 3U)
178
#define UART1_RX_P57 TI_CC32XX_PINMUX(57U, 6U)
179
#define GT_CCP02_P57 TI_CC32XX_PINMUX(57U, 7U)
180
181
#define GPIO3_P58 TI_CC32XX_PINMUX(58U, 0U)
182
#define UART1_TX_P58 TI_CC32XX_PINMUX(58U, 6U)
183
#define PDATA7_P58 TI_CC32XX_PINMUX(58U, 7U)
184
185
#define GPIO5_P59 TI_CC32XX_PINMUX(59U, 0U)
186
#define UART1_RX_P59 TI_CC32XX_PINMUX(59U, 6U)
187
#define PDATA6_P59 TI_CC32XX_PINMUX(59U, 4U)
188
189
#define GPIO5_P60 TI_CC32XX_PINMUX(60U, 0U)
190
#define PDATA5_P60 TI_CC32XX_PINMUX(60U, 4U)
191
#define MCAXR1_P60 TI_CC32XX_PINMUX(60U, 6U)
192
#define GT_CCP05_P60 TI_CC32XX_PINMUX(60U, 7U)
193
194
#define GPIO6_P61 TI_CC32XX_PINMUX(61U, 0U)
195
#define UART0_RTS_P61 TI_CC32XX_PINMUX(61U, 5U)
196
#define PDATA4_P61 TI_CC32XX_PINMUX(61U, 4U)
197
#define UART1_CTS_P61 TI_CC32XX_PINMUX(61U, 3U)
198
#define UART0_CTS_P61 TI_CC32XX_PINMUX(61U, 6U)
199
#define GT_CCP06_P61 TI_CC32XX_PINMUX(61U, 7U)
200
201
#define GPIO7_P62 TI_CC32XX_PINMUX(62U, 0U)
202
#define MCACLKX_P62 TI_CC32XX_PINMUX(62U, 13U)
203
#define UART1_RTS_P62 TI_CC32XX_PINMUX(62U, 3U)
204
#define UART0_RTS_P62 TI_CC32XX_PINMUX(62U, 10U)
205
#define UART0_TX_P62 TI_CC32XX_PINMUX(62U, 11U)
206
207
#define GPIO8_P63 TI_CC32XX_PINMUX(63U, 0U)
208
#define SDCARD_IRQ_P63 TI_CC32XX_PINMUX(63U, 6U)
209
#define MCAFSX_P63 TI_CC32XX_PINMUX(63U, 7U)
210
#define GT_CCP06_P63 TI_CC32XX_PINMUX(63U, 12U)
211
212
#define GPIO9_P64 TI_CC32XX_PINMUX(64U, 0U)
213
#define GT_PWM05_P64 TI_CC32XX_PINMUX(64U, 3U)
214
#define SDCARD_DATA_P64 TI_CC32XX_PINMUX(64U, 6U)
215
#define MCAXR0_P64 TI_CC32XX_PINMUX(64U, 7U)
216
#define GT_CCP00_P64 TI_CC32XX_PINMUX(64U, 12U)
217
220
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_ */
zephyr
dt-bindings
pinctrl
ti-cc32xx-pinctrl.h
Generated on Fri Nov 8 2024 18:02:19 for Zephyr API Documentation by
1.12.0