Zephyr API Documentation
4.0.0-rc3
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test_asm_inline_gcc.h
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/* GCC specific test inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TEST_ASM_INLINE_GCC_H
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#define _TEST_ASM_INLINE_GCC_H
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#include <
zephyr/sys/barrier.h
>
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#if !defined(__GNUC__)
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#error test_asm_inline_gcc.h goes only with GCC
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#endif
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#if defined(CONFIG_X86)
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static
inline
void
timestamp_serialize(
void
)
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{
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__asm__ __volatile__ (
/* serialize */
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"xorl %%eax,%%eax;\n\t"
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"cpuid;\n\t"
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:
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:
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:
"%eax"
,
"%ebx"
,
"%ecx"
,
"%edx"
);
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}
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#elif defined(CONFIG_CPU_CORTEX_M) || \
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defined(CONFIG_CPU_AARCH32_CORTEX_R) || \
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defined(CONFIG_CPU_AARCH32_CORTEX_A) || \
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defined(CONFIG_CPU_CORTEX_A) || \
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defined(CONFIG_CPU_AARCH64_CORTEX_R)
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static
inline
void
timestamp_serialize(
void
)
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{
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barrier_isync_fence_full
();
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}
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#elif defined(CONFIG_ARC)
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#define timestamp_serialize()
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#elif defined(CONFIG_ARCH_POSIX)
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#define timestamp_serialize()
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#elif defined(CONFIG_XTENSA)
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#define timestamp_serialize()
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#elif defined(CONFIG_NIOS2)
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#define timestamp_serialize()
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#elif defined(CONFIG_RISCV)
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#define timestamp_serialize()
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#elif defined(CONFIG_SPARC)
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#define timestamp_serialize()
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#elif defined(CONFIG_MIPS)
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#define timestamp_serialize()
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#else
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#error implementation of timestamp_serialize() not provided for your CPU target
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#endif
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#endif
/* _TEST_ASM_INLINE_GCC_H */
barrier_isync_fence_full
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition
barrier.h:78
barrier.h
subsys
testsuite
include
zephyr
test_asm_inline_gcc.h
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