Zephyr API Documentation
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A Scalable Open Source RTOS
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stm32mp1_reset.h
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/*
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* Copyright (c) 2022 Google Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_
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#define STM32_RESET(bus, bit) \
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(((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
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/* RCC bus reset register offset */
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#define STM32_RESET_BUS_AHB2_SET 0x998
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#define STM32_RESET_BUS_AHB2_CLR 0x99C
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#define STM32_RESET_BUS_AHB3_SET 0x9A0
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#define STM32_RESET_BUS_AHB3_CLR 0x9A4
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#define STM32_RESET_BUS_AHB4_SET 0x9A8
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#define STM32_RESET_BUS_AHB4_CLR 0x9AC
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#define STM32_RESET_BUS_AHB5_SET 0x190
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#define STM32_RESET_BUS_AHB5_CLR 0x194
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#define STM32_RESET_BUS_AHB6_SET 0x198
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#define STM32_RESET_BUS_AHB6_CLR 0x19C
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#define STM32_RESET_BUS_TZAHB6_SET 0x1A0
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#define STM32_RESET_BUS_TZAHB6_CLR 0x1A4
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#define STM32_RESET_BUS_APB1_SET 0x980
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#define STM32_RESET_BUS_APB1_CLR 0x984
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#define STM32_RESET_BUS_APB2_SET 0x988
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#define STM32_RESET_BUS_APB2_CLR 0x98C
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#define STM32_RESET_BUS_APB3_SET 0x990
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#define STM32_RESET_BUS_APB3_CLR 0x994
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#define STM32_RESET_BUS_APB4_SET 0x180
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#define STM32_RESET_BUS_APB4_CLR 0x184
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#define STM32_RESET_BUS_APB5_SET 0x188
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#define STM32_RESET_BUS_APB5_CLR 0x18C
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP1_RESET_H_ */
zephyr
dt-bindings
reset
stm32mp1_reset.h
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