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stm32-fmc-nor-psram.h
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/*
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* Copyright (c) 2022 Georgij Cernysiov
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
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/* Data Address Bus Multiplexing */
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#define STM32_FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000UL
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#define STM32_FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002UL
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/* Memory Type */
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#define STM32_FMC_MEMORY_TYPE_SRAM 0x00000000UL
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#define STM32_FMC_MEMORY_TYPE_PSRAM 0x00000004UL
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#define STM32_FMC_MEMORY_TYPE_NOR 0x00000008UL
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/* NORSRAM Data Width */
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#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000UL
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#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010UL
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#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020UL
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/* Burst Access Mode */
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#define STM32_FMC_BURST_ACCESS_MODE_DISABLE 0x00000000UL
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#define STM32_FMC_BURST_ACCESS_MODE_ENABLE 0x00000100UL
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/* Wait Signal Polarity */
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#define STM32_FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000UL
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#define STM32_FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200UL
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/* Wait Timing */
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#define STM32_FMC_WAIT_TIMING_BEFORE_WS 0x00000000UL
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#define STM32_FMC_WAIT_TIMING_DURING_WS 0x00000800UL
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/* Write Operation */
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#define STM32_FMC_WRITE_OPERATION_DISABLE 0x00000000UL
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#define STM32_FMC_WRITE_OPERATION_ENABLE 0x00001000UL
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/* Wait Signal */
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#define STM32_FMC_WAIT_SIGNAL_DISABLE 0x00000000UL
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#define STM32_FMC_WAIT_SIGNAL_ENABLE 0x00002000UL
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/* Extended Mode */
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#define STM32_FMC_EXTENDED_MODE_DISABLE 0x00000000UL
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#define STM32_FMC_EXTENDED_MODE_ENABLE 0x00004000UL
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/* Asynchronous Wait */
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#define STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000UL
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#define STM32_FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000UL
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/* Write Burst */
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#define STM32_FMC_WRITE_BURST_DISABLE 0x00000000UL
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#define STM32_FMC_WRITE_BURST_ENABLE 0x00080000UL
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/* Continuous Clock */
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#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000UL
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#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000UL
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/* Write FIFO */
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/* Not every SoC can disable FIFO, refer to reference manual */
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#define STM32_FMC_WRITE_FIFO_DISABLE 0x00200000UL
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#define STM32_FMC_WRITE_FIFO_ENABLE 0x00000000UL
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/* Page Size */
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#define STM32_FMC_PAGE_SIZE_NONE 0x00000000UL
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#define STM32_FMC_PAGE_SIZE_128 0x00010000UL
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#define STM32_FMC_PAGE_SIZE_256 0x00020000UL
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#define STM32_FMC_PAGE_SIZE_512 0x00030000UL
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#define STM32_FMC_PAGE_SIZE_1024 0x00040000UL
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/* Access Mode */
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#define STM32_FMC_ACCESS_MODE_A 0x00000000UL
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#define STM32_FMC_ACCESS_MODE_B 0x10000000UL
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#define STM32_FMC_ACCESS_MODE_C 0x20000000UL
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#define STM32_FMC_ACCESS_MODE_D 0x30000000UL
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ */
zephyr
dt-bindings
memory-controller
stm32-fmc-nor-psram.h
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