Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32-fmc-nor-psram.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022 Georgij Cernysiov
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
7
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
8
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
9
10
/* Data Address Bus Multiplexing */
11
#define STM32_FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000UL
12
#define STM32_FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002UL
13
14
/* Memory Type */
15
#define STM32_FMC_MEMORY_TYPE_SRAM 0x00000000UL
16
#define STM32_FMC_MEMORY_TYPE_PSRAM 0x00000004UL
17
#define STM32_FMC_MEMORY_TYPE_NOR 0x00000008UL
18
19
/* NORSRAM Data Width */
20
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000UL
21
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010UL
22
#define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020UL
23
24
/* Burst Access Mode */
25
#define STM32_FMC_BURST_ACCESS_MODE_DISABLE 0x00000000UL
26
#define STM32_FMC_BURST_ACCESS_MODE_ENABLE 0x00000100UL
27
28
/* Wait Signal Polarity */
29
#define STM32_FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000UL
30
#define STM32_FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200UL
31
32
/* Wait Timing */
33
#define STM32_FMC_WAIT_TIMING_BEFORE_WS 0x00000000UL
34
#define STM32_FMC_WAIT_TIMING_DURING_WS 0x00000800UL
35
36
/* Write Operation */
37
#define STM32_FMC_WRITE_OPERATION_DISABLE 0x00000000UL
38
#define STM32_FMC_WRITE_OPERATION_ENABLE 0x00001000UL
39
40
/* Wait Signal */
41
#define STM32_FMC_WAIT_SIGNAL_DISABLE 0x00000000UL
42
#define STM32_FMC_WAIT_SIGNAL_ENABLE 0x00002000UL
43
44
/* Extended Mode */
45
#define STM32_FMC_EXTENDED_MODE_DISABLE 0x00000000UL
46
#define STM32_FMC_EXTENDED_MODE_ENABLE 0x00004000UL
47
48
/* Asynchronous Wait */
49
#define STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000UL
50
#define STM32_FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000UL
51
52
/* Write Burst */
53
#define STM32_FMC_WRITE_BURST_DISABLE 0x00000000UL
54
#define STM32_FMC_WRITE_BURST_ENABLE 0x00080000UL
55
56
/* Continuous Clock */
57
#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000UL
58
#define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000UL
59
60
/* Write FIFO */
61
/* Not every SoC can disable FIFO, refer to reference manual */
62
#define STM32_FMC_WRITE_FIFO_DISABLE 0x00200000UL
63
#define STM32_FMC_WRITE_FIFO_ENABLE 0x00000000UL
64
65
/* Page Size */
66
#define STM32_FMC_PAGE_SIZE_NONE 0x00000000UL
67
#define STM32_FMC_PAGE_SIZE_128 0x00010000UL
68
#define STM32_FMC_PAGE_SIZE_256 0x00020000UL
69
#define STM32_FMC_PAGE_SIZE_512 0x00030000UL
70
#define STM32_FMC_PAGE_SIZE_1024 0x00040000UL
71
72
/* Access Mode */
73
#define STM32_FMC_ACCESS_MODE_A 0x00000000UL
74
#define STM32_FMC_ACCESS_MODE_B 0x10000000UL
75
#define STM32_FMC_ACCESS_MODE_C 0x20000000UL
76
#define STM32_FMC_ACCESS_MODE_D 0x30000000UL
77
78
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ */
zephyr
dt-bindings
memory-controller
stm32-fmc-nor-psram.h
Generated on Fri Nov 8 2024 21:02:38 for Zephyr API Documentation by
1.12.0