Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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qdec_nxp_s32.h
Go to the documentation of this file.
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Logic Trigger Numbers. See Trgmux_Ip_Init_PBcfg.h */
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#define TRGMUX_LOGIC_GROUP_0_TRIGGER_0 (0)
/* Logic Trigger 0 */
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#define TRGMUX_LOGIC_GROUP_0_TRIGGER_1 (1)
/* Logic Trigger 1 */
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#define TRGMUX_LOGIC_GROUP_1_TRIGGER_0 (2)
/* Logic Trigger 2 */
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#define TRGMUX_LOGIC_GROUP_1_TRIGGER_1 (3)
/* Logic Trigger 3 */
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/*-----------------------------------------------
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* TRGMUX HARDWARE TRIGGER INPUT
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* See Trgmux_Ip_Cfg_Defines.h
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*-----------------------------------------------
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*/
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#define TRGMUX_IP_INPUT_SIUL2_IN0 (60)
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#define TRGMUX_IP_INPUT_SIUL2_IN1 (61)
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#define TRGMUX_IP_INPUT_SIUL2_IN2 (62)
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#define TRGMUX_IP_INPUT_SIUL2_IN3 (63)
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#define TRGMUX_IP_INPUT_SIUL2_IN4 (64)
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#define TRGMUX_IP_INPUT_SIUL2_IN5 (65)
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#define TRGMUX_IP_INPUT_SIUL2_IN6 (66)
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#define TRGMUX_IP_INPUT_SIUL2_IN7 (67)
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#define TRGMUX_IP_INPUT_SIUL2_IN8 (68)
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#define TRGMUX_IP_INPUT_SIUL2_IN9 (69)
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#define TRGMUX_IP_INPUT_SIUL2_IN10 (70)
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#define TRGMUX_IP_INPUT_SIUL2_IN11 (71)
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#define TRGMUX_IP_INPUT_SIUL2_IN12 (72)
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#define TRGMUX_IP_INPUT_SIUL2_IN13 (73)
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#define TRGMUX_IP_INPUT_SIUL2_IN14 (74)
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#define TRGMUX_IP_INPUT_SIUL2_IN15 (75)
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#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I0 (105)
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#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I1 (106)
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#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2 (107)
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#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3 (108)
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/*-----------------------------------------------
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* TRGMUX HARDWARE TRIGGER OUTPUT
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* See Trgmux_Ip_Cfg_Defines.h
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*-----------------------------------------------
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*/
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#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 (144)
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#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 (145)
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#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I2 (146)
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#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I3 (147)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH1 (32)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH2 (33)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH3 (34)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH4 (35)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH5 (36)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 (37)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 (38)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH9 (39)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH10 (40)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH11 (41)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH12 (42)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH13 (43)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH14 (44)
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#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH15 (45)
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/*-----------------------------------------------
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* LCU SOURCE MUX SELECT
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* See Lcu_Ip_Cfg_Defines.h
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*-----------------------------------------------
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*/
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#define LCU_IP_MUX_SEL_LOGIC_0 (0)
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#define LCU_IP_MUX_SEL_LU_IN_0 (1)
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#define LCU_IP_MUX_SEL_LU_IN_1 (2)
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#define LCU_IP_MUX_SEL_LU_IN_2 (3)
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#define LCU_IP_MUX_SEL_LU_IN_3 (4)
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#define LCU_IP_MUX_SEL_LU_IN_4 (5)
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#define LCU_IP_MUX_SEL_LU_IN_5 (6)
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#define LCU_IP_MUX_SEL_LU_IN_6 (7)
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#define LCU_IP_MUX_SEL_LU_IN_7 (8)
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#define LCU_IP_MUX_SEL_LU_IN_8 (9)
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#define LCU_IP_MUX_SEL_LU_IN_9 (10)
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#define LCU_IP_MUX_SEL_LU_IN_10 (11)
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#define LCU_IP_MUX_SEL_LU_IN_11 (12)
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#define LCU_IP_MUX_SEL_LU_OUT_0 (13)
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#define LCU_IP_MUX_SEL_LU_OUT_1 (14)
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#define LCU_IP_MUX_SEL_LU_OUT_2 (15)
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#define LCU_IP_MUX_SEL_LU_OUT_3 (16)
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#define LCU_IP_MUX_SEL_LU_OUT_4 (17)
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#define LCU_IP_MUX_SEL_LU_OUT_5 (18)
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#define LCU_IP_MUX_SEL_LU_OUT_6 (19)
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#define LCU_IP_MUX_SEL_LU_OUT_7 (20)
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#define LCU_IP_MUX_SEL_LU_OUT_8 (21)
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#define LCU_IP_MUX_SEL_LU_OUT_9 (22)
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#define LCU_IP_MUX_SEL_LU_OUT_10 (23)
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#define LCU_IP_MUX_SEL_LU_OUT_11 (24)
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#define LCU_IP_IN_0 (0)
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#define LCU_IP_IN_1 (1)
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#define LCU_IP_IN_2 (2)
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#define LCU_IP_IN_3 (3)
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#define LCU_IP_IN_4 (4)
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#define LCU_IP_IN_5 (5)
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#define LCU_IP_IN_6 (6)
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#define LCU_IP_IN_7 (7)
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#define LCU_IP_IN_8 (8)
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#define LCU_IP_IN_9 (9)
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#define LCU_IP_IN_10 (10)
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#define LCU_IP_IN_11 (11)
zephyr
dt-bindings
sensor
qdec_nxp_s32.h
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