Zephyr API Documentation
4.0.0-rc3
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
qdec_nxp_s32.h
Go to the documentation of this file.
1
/*
2
* Copyright 2023 NXP
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
7
/* Logic Trigger Numbers. See Trgmux_Ip_Init_PBcfg.h */
8
#define TRGMUX_LOGIC_GROUP_0_TRIGGER_0 (0)
/* Logic Trigger 0 */
9
#define TRGMUX_LOGIC_GROUP_0_TRIGGER_1 (1)
/* Logic Trigger 1 */
10
#define TRGMUX_LOGIC_GROUP_1_TRIGGER_0 (2)
/* Logic Trigger 2 */
11
#define TRGMUX_LOGIC_GROUP_1_TRIGGER_1 (3)
/* Logic Trigger 3 */
12
13
/*-----------------------------------------------
14
* TRGMUX HARDWARE TRIGGER INPUT
15
* See Trgmux_Ip_Cfg_Defines.h
16
*-----------------------------------------------
17
*/
18
#define TRGMUX_IP_INPUT_SIUL2_IN0 (60)
19
#define TRGMUX_IP_INPUT_SIUL2_IN1 (61)
20
#define TRGMUX_IP_INPUT_SIUL2_IN2 (62)
21
#define TRGMUX_IP_INPUT_SIUL2_IN3 (63)
22
#define TRGMUX_IP_INPUT_SIUL2_IN4 (64)
23
#define TRGMUX_IP_INPUT_SIUL2_IN5 (65)
24
#define TRGMUX_IP_INPUT_SIUL2_IN6 (66)
25
#define TRGMUX_IP_INPUT_SIUL2_IN7 (67)
26
#define TRGMUX_IP_INPUT_SIUL2_IN8 (68)
27
#define TRGMUX_IP_INPUT_SIUL2_IN9 (69)
28
#define TRGMUX_IP_INPUT_SIUL2_IN10 (70)
29
#define TRGMUX_IP_INPUT_SIUL2_IN11 (71)
30
#define TRGMUX_IP_INPUT_SIUL2_IN12 (72)
31
#define TRGMUX_IP_INPUT_SIUL2_IN13 (73)
32
#define TRGMUX_IP_INPUT_SIUL2_IN14 (74)
33
#define TRGMUX_IP_INPUT_SIUL2_IN15 (75)
34
35
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I0 (105)
36
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I1 (106)
37
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2 (107)
38
#define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3 (108)
39
40
/*-----------------------------------------------
41
* TRGMUX HARDWARE TRIGGER OUTPUT
42
* See Trgmux_Ip_Cfg_Defines.h
43
*-----------------------------------------------
44
*/
45
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 (144)
46
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 (145)
47
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I2 (146)
48
#define TRGMUX_IP_OUTPUT_LCU1_0_INP_I3 (147)
49
50
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH1 (32)
51
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH2 (33)
52
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH3 (34)
53
#define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH4 (35)
54
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH5 (36)
55
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 (37)
56
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 (38)
57
#define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH9 (39)
58
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH10 (40)
59
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH11 (41)
60
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH12 (42)
61
#define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH13 (43)
62
#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH14 (44)
63
#define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH15 (45)
64
65
/*-----------------------------------------------
66
* LCU SOURCE MUX SELECT
67
* See Lcu_Ip_Cfg_Defines.h
68
*-----------------------------------------------
69
*/
70
#define LCU_IP_MUX_SEL_LOGIC_0 (0)
71
#define LCU_IP_MUX_SEL_LU_IN_0 (1)
72
#define LCU_IP_MUX_SEL_LU_IN_1 (2)
73
#define LCU_IP_MUX_SEL_LU_IN_2 (3)
74
#define LCU_IP_MUX_SEL_LU_IN_3 (4)
75
#define LCU_IP_MUX_SEL_LU_IN_4 (5)
76
#define LCU_IP_MUX_SEL_LU_IN_5 (6)
77
#define LCU_IP_MUX_SEL_LU_IN_6 (7)
78
#define LCU_IP_MUX_SEL_LU_IN_7 (8)
79
#define LCU_IP_MUX_SEL_LU_IN_8 (9)
80
#define LCU_IP_MUX_SEL_LU_IN_9 (10)
81
#define LCU_IP_MUX_SEL_LU_IN_10 (11)
82
#define LCU_IP_MUX_SEL_LU_IN_11 (12)
83
#define LCU_IP_MUX_SEL_LU_OUT_0 (13)
84
#define LCU_IP_MUX_SEL_LU_OUT_1 (14)
85
#define LCU_IP_MUX_SEL_LU_OUT_2 (15)
86
#define LCU_IP_MUX_SEL_LU_OUT_3 (16)
87
#define LCU_IP_MUX_SEL_LU_OUT_4 (17)
88
#define LCU_IP_MUX_SEL_LU_OUT_5 (18)
89
#define LCU_IP_MUX_SEL_LU_OUT_6 (19)
90
#define LCU_IP_MUX_SEL_LU_OUT_7 (20)
91
#define LCU_IP_MUX_SEL_LU_OUT_8 (21)
92
#define LCU_IP_MUX_SEL_LU_OUT_9 (22)
93
#define LCU_IP_MUX_SEL_LU_OUT_10 (23)
94
#define LCU_IP_MUX_SEL_LU_OUT_11 (24)
95
96
#define LCU_IP_IN_0 (0)
97
#define LCU_IP_IN_1 (1)
98
#define LCU_IP_IN_2 (2)
99
#define LCU_IP_IN_3 (3)
100
#define LCU_IP_IN_4 (4)
101
#define LCU_IP_IN_5 (5)
102
#define LCU_IP_IN_6 (6)
103
#define LCU_IP_IN_7 (7)
104
#define LCU_IP_IN_8 (8)
105
#define LCU_IP_IN_9 (9)
106
#define LCU_IP_IN_10 (10)
107
#define LCU_IP_IN_11 (11)
zephyr
dt-bindings
sensor
qdec_nxp_s32.h
Generated on Tue Nov 12 2024 18:02:54 for Zephyr API Documentation by
1.12.0