Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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pinctrl-rcar-common.h
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/*
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* Copyright (c) 2021-2023 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
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#define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
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/* Arbitrary number to encode non capable gpio pin */
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#define PIN_NOGPSR_START 1024U
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#define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin))
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#define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin)
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/* Renesas Gen4 has IPSR registers at different base address
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* reg is here an index for the base address.
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* Each base address has 4 IPSR banks.
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*/
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#define IPnSR(bank, reg, shift, func) \
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IPSR(((reg) << 5U) | (bank), shift, func)
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#define IP0SR0(shift, func) IPnSR(0, 0, shift, func)
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#define IP1SR0(shift, func) IPnSR(1, 0, shift, func)
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#define IP2SR0(shift, func) IPnSR(2, 0, shift, func)
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#define IP3SR0(shift, func) IPnSR(3, 0, shift, func)
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#define IP0SR1(shift, func) IPnSR(0, 1, shift, func)
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#define IP1SR1(shift, func) IPnSR(1, 1, shift, func)
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#define IP2SR1(shift, func) IPnSR(2, 1, shift, func)
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#define IP3SR1(shift, func) IPnSR(3, 1, shift, func)
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#define IP0SR2(shift, func) IPnSR(0, 2, shift, func)
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#define IP1SR2(shift, func) IPnSR(1, 2, shift, func)
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#define IP2SR2(shift, func) IPnSR(2, 2, shift, func)
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#define IP3SR2(shift, func) IPnSR(3, 2, shift, func)
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#define IP0SR3(shift, func) IPnSR(0, 3, shift, func)
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#define IP1SR3(shift, func) IPnSR(1, 3, shift, func)
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#define IP2SR3(shift, func) IPnSR(2, 3, shift, func)
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#define IP3SR3(shift, func) IPnSR(3, 3, shift, func)
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#define IP0SR4(shift, func) IPnSR(0, 4, shift, func)
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#define IP1SR4(shift, func) IPnSR(1, 4, shift, func)
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#define IP2SR4(shift, func) IPnSR(2, 4, shift, func)
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#define IP3SR4(shift, func) IPnSR(3, 4, shift, func)
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#define IP0SR5(shift, func) IPnSR(0, 5, shift, func)
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#define IP1SR5(shift, func) IPnSR(1, 5, shift, func)
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#define IP2SR5(shift, func) IPnSR(2, 5, shift, func)
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#define IP3SR5(shift, func) IPnSR(3, 5, shift, func)
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#define IP0SR6(shift, func) IPnSR(0, 6, shift, func)
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#define IP1SR6(shift, func) IPnSR(1, 6, shift, func)
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#define IP2SR6(shift, func) IPnSR(2, 6, shift, func)
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#define IP3SR6(shift, func) IPnSR(3, 6, shift, func)
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#define IP0SR7(shift, func) IPnSR(0, 7, shift, func)
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#define IP1SR7(shift, func) IPnSR(1, 7, shift, func)
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#define IP2SR7(shift, func) IPnSR(2, 7, shift, func)
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#define IP3SR7(shift, func) IPnSR(3, 7, shift, func)
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#define IPSR_DUMMY IPnSR(0x1f, 7, 0x1f, 0xf)
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#define PIN_VOLTAGE_NONE 0
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#define PIN_VOLTAGE_1P8V 1
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#define PIN_VOLTAGE_3P3V 2
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */
zephyr
dt-bindings
pinctrl
renesas
pinctrl-rcar-common.h
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