13#ifndef ZEPHYR_INCLUDE_DRIVERS_PECI_H_ 
   14#define ZEPHYR_INCLUDE_DRIVERS_PECI_H_ 
   74#define PECI_CC_RSP_SUCCESS              (0x40U) 
   75#define PECI_CC_RSP_TIMEOUT              (0x80U) 
   76#define PECI_CC_OUT_OF_RESOURCES_TIMEOUT (0x81U) 
   77#define PECI_CC_RESOURCES_LOWPWR_TIMEOUT (0x82U) 
   78#define PECI_CC_ILLEGAL_REQUEST          (0x90U) 
   85#define PECI_PING_WR_LEN               (0U) 
   86#define PECI_PING_RD_LEN               (0U) 
   87#define PECI_PING_LEN                  (3U) 
   94#define PECI_GET_DIB_WR_LEN            (1U) 
   95#define PECI_GET_DIB_RD_LEN            (8U) 
   96#define PECI_GET_DIB_CMD_LEN           (4U) 
   97#define PECI_GET_DIB_DEVINFO           (0U) 
   98#define PECI_GET_DIB_REVNUM            (1U) 
   99#define PECI_GET_DIB_DOMAIN_BIT_MASK   (0x4U) 
  100#define PECI_GET_DIB_MAJOR_REV_MASK    0xF0 
  101#define PECI_GET_DIB_MINOR_REV_MASK    0x0F 
  108#define PECI_GET_TEMP_WR_LEN           (1U) 
  109#define PECI_GET_TEMP_RD_LEN           (2U) 
  110#define PECI_GET_TEMP_CMD_LEN          (4U) 
  111#define PECI_GET_TEMP_LSB              (0U) 
  112#define PECI_GET_TEMP_MSB              (1U) 
  113#define PECI_GET_TEMP_ERR_MSB          (0x80U) 
  114#define PECI_GET_TEMP_ERR_LSB_GENERAL  (0x0U) 
  115#define PECI_GET_TEMP_ERR_LSB_RES      (0x1U) 
  116#define PECI_GET_TEMP_ERR_LSB_TEMP_LO  (0x2U) 
  117#define PECI_GET_TEMP_ERR_LSB_TEMP_HI  (0x3U) 
  124#define PECI_RD_PKG_WR_LEN             (5U) 
  125#define PECI_RD_PKG_LEN_BYTE           (2U) 
  126#define PECI_RD_PKG_LEN_WORD           (3U) 
  127#define PECI_RD_PKG_LEN_DWORD          (5U) 
  128#define PECI_RD_PKG_CMD_LEN            (8U) 
  135#define PECI_WR_PKG_RD_LEN              (1U) 
  136#define PECI_WR_PKG_LEN_BYTE            (7U) 
  137#define PECI_WR_PKG_LEN_WORD            (8U) 
  138#define PECI_WR_PKG_LEN_DWORD           (10U) 
  139#define PECI_WR_PKG_CMD_LEN             (9U) 
  146#define PECI_RD_IAMSR_WR_LEN            (5U) 
  147#define PECI_RD_IAMSR_LEN_BYTE          (2U) 
  148#define PECI_RD_IAMSR_LEN_WORD          (3U) 
  149#define PECI_RD_IAMSR_LEN_DWORD         (5U) 
  150#define PECI_RD_IAMSR_LEN_QWORD         (9U) 
  151#define PECI_RD_IAMSR_CMD_LEN           (8U) 
  158#define PECI_WR_IAMSR_RD_LEN            (1U) 
  159#define PECI_WR_IAMSR_LEN_BYTE          (7U) 
  160#define PECI_WR_IAMSR_LEN_WORD          (8U) 
  161#define PECI_WR_IAMSR_LEN_DWORD         (10U) 
  162#define PECI_WR_IAMSR_LEN_QWORD         (14U) 
  163#define PECI_WR_IAMSR_CMD_LEN           (9U) 
  170#define PECI_RD_PCICFG_WR_LEN           (6U) 
  171#define PECI_RD_PCICFG_LEN_BYTE         (2U) 
  172#define PECI_RD_PCICFG_LEN_WORD         (3U) 
  173#define PECI_RD_PCICFG_LEN_DWORD        (5U) 
  174#define PECI_RD_PCICFG_CMD_LEN          (9U) 
  181#define PECI_WR_PCICFG_RD_LEN           (1U) 
  182#define PECI_WR_PCICFG_LEN_BYTE         (8U) 
  183#define PECI_WR_PCICFG_LEN_WORD         (9U) 
  184#define PECI_WR_PCICFG_LEN_DWORD        (11U) 
  185#define PECI_WR_PCICFG_CMD_LEN          (10U) 
  192#define PECI_RD_PCICFGL_WR_LEN          (5U) 
  193#define PECI_RD_PCICFGL_RD_LEN_BYTE     (2U) 
  194#define PECI_RD_PCICFGL_RD_LEN_WORD     (3U) 
  195#define PECI_RD_PCICFGL_RD_LEN_DWORD    (5U) 
  196#define PECI_RD_PCICFGL_CMD_LEN         (8U) 
  203#define PECI_WR_PCICFGL_RD_LEN          (1U) 
  204#define PECI_WR_PCICFGL_WR_LEN_BYTE     (7U) 
  205#define PECI_WR_PCICFGL_WR_LEN_WORD     (8U) 
  206#define PECI_WR_PCICFGL_WR_LEN_DWORD    (10U) 
  207#define PECI_WR_PCICFGL_CMD_LEN         (9U) 
  251typedef int (*peci_config_t)(
const struct device *dev, 
uint32_t bitrate);
 
  252typedef int (*peci_transfer_t)(
const struct device *dev, 
struct peci_msg *msg);
 
  253typedef int (*peci_disable_t)(
const struct device *dev);
 
  254typedef int (*peci_enable_t)(
const struct device *dev);
 
  256__subsystem 
struct peci_driver_api {
 
  257        peci_config_t config;
 
  258        peci_disable_t disable;
 
  259        peci_enable_t enable;
 
  260        peci_transfer_t transfer;
 
  278static inline int z_impl_peci_config(
const struct device *dev,
 
  281        struct peci_driver_api *api;
 
  283        api = (
struct peci_driver_api *)dev->
api;
 
  284        return api->config(dev, bitrate);
 
  297static inline int z_impl_peci_enable(
const struct device *dev)
 
  299        struct peci_driver_api *api;
 
  301        api = (
struct peci_driver_api *)dev->
api;
 
  302        return api->enable(dev);
 
  315static inline int z_impl_peci_disable(
const struct device *dev)
 
  317        struct peci_driver_api *api;
 
  319        api = (
struct peci_driver_api *)dev->
api;
 
  320        return api->disable(dev);
 
  335static inline int z_impl_peci_transfer(
const struct device *dev,
 
  338        struct peci_driver_api *api;
 
  340        api = (
struct peci_driver_api *)dev->
api;
 
  341        return api->transfer(dev, msg);
 
  353#include <zephyr/syscalls/peci.h> 
peci_error_code
PECI error codes.
Definition peci.h:38
 
int peci_config(const struct device *dev, uint32_t bitrate)
Configures the PECI interface.
 
int peci_enable(const struct device *dev)
Enable PECI interface.
 
peci_command_code
PECI commands.
Definition peci.h:47
 
int peci_transfer(const struct device *dev, struct peci_msg *msg)
Performs a PECI transaction.
 
int peci_disable(const struct device *dev)
Disable PECI interface.
 
@ PECI_UNDERFLOW_SENSOR_ERROR
Definition peci.h:40
 
@ PECI_GENERAL_SENSOR_ERROR
Definition peci.h:39
 
@ PECI_OVERFLOW_SENSOR_ERROR
Definition peci.h:41
 
@ PECI_CMD_GET_DIB
Definition peci.h:67
 
@ PECI_CMD_GET_TEMP1
Definition peci.h:50
 
@ PECI_CMD_RD_PCI_CFG_LOCAL0
Definition peci.h:63
 
@ PECI_CMD_RD_PKG_CFG1
Definition peci.h:56
 
@ PECI_CMD_WR_IAMSR0
Definition peci.h:61
 
@ PECI_CMD_WR_PKG_CFG1
Definition peci.h:58
 
@ PECI_CMD_RD_PKG_CFG0
Definition peci.h:55
 
@ PECI_CMD_WR_PCI_CFG1
Definition peci.h:54
 
@ PECI_CMD_RD_IAMSR1
Definition peci.h:60
 
@ PECI_CMD_RD_PCI_CFG1
Definition peci.h:52
 
@ PECI_CMD_WR_PCI_CFG_LOCAL1
Definition peci.h:66
 
@ PECI_CMD_RD_PCI_CFG0
Definition peci.h:51
 
@ PECI_CMD_WR_IAMSR1
Definition peci.h:62
 
@ PECI_CMD_WR_PKG_CFG0
Definition peci.h:57
 
@ PECI_CMD_WR_PCI_CFG0
Definition peci.h:53
 
@ PECI_CMD_RD_PCI_CFG_LOCAL1
Definition peci.h:64
 
@ PECI_CMD_RD_IAMSR0
Definition peci.h:59
 
@ PECI_CMD_PING
Definition peci.h:48
 
@ PECI_CMD_WR_PCI_CFG_LOCAL0
Definition peci.h:65
 
@ PECI_CMD_GET_TEMP0
Definition peci.h:49
 
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
 
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
 
Runtime device structure (in ROM) per driver instance.
Definition device.h:510
 
const void * api
Address of the API structure exposed by the device instance.
Definition device.h:516
 
PECI buffer structure.
Definition peci.h:213
 
size_t len
Length of the data buffer expected to be received without considering the frame check sequence byte.
Definition peci.h:225
 
uint8_t * buf
Valid pointer on a data buffer, or NULL otherwise.
Definition peci.h:217
 
PECI transaction packet format.
Definition peci.h:231
 
uint8_t flags
PECI msg flags.
Definition peci.h:241
 
enum peci_command_code cmd_code
Command code.
Definition peci.h:235
 
struct peci_buf tx_buffer
Pointer to buffer of write data.
Definition peci.h:237
 
uint8_t addr
Client address.
Definition peci.h:233
 
struct peci_buf rx_buffer
Pointer to buffer of read data.
Definition peci.h:239