10#define FLEXRAM_DT_NODE DT_INST(0, nxp_flexram)
11#define IOMUXC_GPR_DT_NODE DT_NODELABEL(iomuxcgpr)
13#if defined(CONFIG_NXP_FLEXRAM_MAGIC_ADDR_API) || \
14 defined(CONFIG_NXP_FLEXRAM_ERROR_INTERRUPT)
15#define FLEXRAM_INTERRUPTS_USED
18#if DT_PROP_HAS_IDX(FLEXRAM_DT_NODE, flexram_bank_spec, 0)
19#define FLEXRAM_RUNTIME_BANKS_USED 1
22#ifdef FLEXRAM_INTERRUPTS_USED
23enum flexram_interrupt_cause {
24#ifdef CONFIG_NXP_FLEXRAM_ERROR_INTERRUPT
25 flexram_ocram_access_error,
26 flexram_itcm_access_error,
27 flexram_dtcm_access_error,
29#ifdef CONFIG_NXP_FLEXRAM_MAGIC_ADDR_API
30 flexram_ocram_magic_addr,
31 flexram_itcm_magic_addr,
32 flexram_dtcm_magic_addr,
36typedef void (*flexram_callback_t)(
enum flexram_interrupt_cause,
void *user_data);
38void flexram_register_callback(flexram_callback_t callback,
void *user_data);
41#ifdef FLEXRAM_RUNTIME_BANKS_USED
47#define GPR_FLEXRAM_REG_FILL(node_id, prop, idx) \
48 (((uint32_t)DT_PROP_BY_IDX(node_id, prop, idx)) << (2 * idx))
49static inline void flexram_dt_partition(
void)
52 static IOMUXC_GPR_Type *
const iomuxc_gpr =
55#if defined(CONFIG_SOC_SERIES_IMXRT11XX)
57 GPR_FLEXRAM_REG_FILL, (+))) & 0xFFFF;
59 GPR_FLEXRAM_REG_FILL, (+)))) >> 16) & 0xFFFF;
60#elif defined(CONFIG_SOC_SERIES_IMXRT10XX)
62 GPR_FLEXRAM_REG_FILL, (+));
64 iomuxc_gpr->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
68#ifdef CONFIG_NXP_FLEXRAM_MAGIC_ADDR_API
79int flexram_set_ocram_magic_addr(
uint32_t ocram_addr);
91int flexram_set_itcm_magic_addr(
uint32_t itcm_addr);
103int flexram_set_dtcm_magic_addr(
uint32_t dtcm_addr);
#define DT_FOREACH_PROP_ELEM_SEP(node_id, prop, fn, sep)
Invokes fn for each element in the value of property prop with separator.
Definition devicetree.h:3367
#define DT_REG_ADDR(node_id)
Get a node's (only) register block address.
Definition devicetree.h:2461
#define FLEXRAM_DT_NODE
Definition nxp_flexram.h:10
#define IOMUXC_GPR_DT_NODE
Definition nxp_flexram.h:11
__UINT32_TYPE__ uint32_t
Definition stdint.h:90