Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
nxp-s32-pinctrl.h
Go to the documentation of this file.
1
/*
2
* Copyright 2022, 2024 NXP
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
7
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
8
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
9
10
#include <
zephyr/dt-bindings/dt-util.h
>
11
12
/*
13
* The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
14
*
15
* - 0..2: Output mux Source Signal Selection (MSCR.SSS)
16
* - 3..6: Input mux Source Signal Selection (IMCR.SSS)
17
* - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index
18
* - 16..24: Multiplexed Signal Configuration Register (MSCR) index
19
* - 25..27: MSCR SIUL2 instance index (0..7)
20
* - 28..30: IMCR SIUL2 instance index (0..7)
21
* - 31: Reserved for future use
22
*/
23
#define NXP_S32_MSCR_SSS_SHIFT 0U
24
#define NXP_S32_MSCR_SSS_MASK BIT_MASK(3)
25
#define NXP_S32_IMCR_SSS_SHIFT 3U
26
#define NXP_S32_IMCR_SSS_MASK BIT_MASK(4)
27
#define NXP_S32_IMCR_IDX_SHIFT 7U
28
#define NXP_S32_IMCR_IDX_MASK BIT_MASK(9)
29
#define NXP_S32_MSCR_IDX_SHIFT 16U
30
#define NXP_S32_MSCR_IDX_MASK BIT_MASK(9)
31
#define NXP_S32_MSCR_SIUL2_IDX_SHIFT 25U
32
#define NXP_S32_MSCR_SIUL2_IDX_MASK BIT_MASK(3)
33
#define NXP_S32_IMCR_SIUL2_IDX_SHIFT 28U
34
#define NXP_S32_IMCR_SIUL2_IDX_MASK BIT_MASK(3)
35
36
#define NXP_S32_PINMUX_MSCR_SSS(cfg) \
37
(((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
38
39
#define NXP_S32_PINMUX_IMCR_SSS(cfg) \
40
(((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
41
42
#define NXP_S32_PINMUX_IMCR_IDX(cfg) \
43
(((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
44
45
#define NXP_S32_PINMUX_MSCR_IDX(cfg) \
46
(((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
47
48
#define NXP_S32_PINMUX_MSCR_SIUL2_IDX(cfg) \
49
(((cfg) & NXP_S32_MSCR_SIUL2_IDX_MASK) << NXP_S32_MSCR_SIUL2_IDX_SHIFT)
50
51
#define NXP_S32_PINMUX_IMCR_SIUL2_IDX(cfg) \
52
(((cfg) & NXP_S32_IMCR_SIUL2_IDX_MASK) << NXP_S32_IMCR_SIUL2_IDX_SHIFT)
53
54
#define NXP_S32_PINMUX_GET_MSCR_SSS(cfg) \
55
(((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK)
56
57
#define NXP_S32_PINMUX_GET_IMCR_SSS(cfg) \
58
(((cfg) >> NXP_S32_IMCR_SSS_SHIFT) & NXP_S32_IMCR_SSS_MASK)
59
60
#define NXP_S32_PINMUX_GET_IMCR_IDX(cfg) \
61
(((cfg) >> NXP_S32_IMCR_IDX_SHIFT) & NXP_S32_IMCR_IDX_MASK)
62
63
#define NXP_S32_PINMUX_GET_MSCR_IDX(cfg) \
64
(((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK)
65
66
#define NXP_S32_PINMUX_GET_MSCR_SIUL2_IDX(cfg) \
67
(((cfg) >> NXP_S32_MSCR_SIUL2_IDX_SHIFT) & NXP_S32_MSCR_SIUL2_IDX_MASK)
68
69
#define NXP_S32_PINMUX_GET_IMCR_SIUL2_IDX(cfg) \
70
(((cfg) >> NXP_S32_IMCR_SIUL2_IDX_SHIFT) & NXP_S32_IMCR_SIUL2_IDX_MASK)
71
82
#define NXP_S32_PINMUX(mscr_siul2_idx, imcr_siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \
83
(NXP_S32_PINMUX_MSCR_SIUL2_IDX(mscr_siul2_idx) | \
84
NXP_S32_PINMUX_IMCR_SIUL2_IDX(imcr_siul2_idx) | \
85
NXP_S32_PINMUX_MSCR_IDX(mscr_idx) | \
86
NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | \
87
NXP_S32_PINMUX_IMCR_IDX(imcr_idx) | \
88
NXP_S32_PINMUX_IMCR_SSS(imcr_sss))
89
90
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */
dt-util.h
zephyr
dt-bindings
pinctrl
nxp-s32-pinctrl.h
Generated on Sat Nov 23 2024 03:10:36 for Zephyr API Documentation by
1.12.0