Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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nxp-s32-pinctrl.h
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/*
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* Copyright 2022, 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_
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#include <
zephyr/dt-bindings/dt-util.h
>
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/*
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* The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows:
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*
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* - 0..2: Output mux Source Signal Selection (MSCR.SSS)
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* - 3..6: Input mux Source Signal Selection (IMCR.SSS)
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* - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index
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* - 16..24: Multiplexed Signal Configuration Register (MSCR) index
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* - 25..27: MSCR SIUL2 instance index (0..7)
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* - 28..30: IMCR SIUL2 instance index (0..7)
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* - 31: Reserved for future use
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*/
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#define NXP_S32_MSCR_SSS_SHIFT 0U
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#define NXP_S32_MSCR_SSS_MASK BIT_MASK(3)
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#define NXP_S32_IMCR_SSS_SHIFT 3U
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#define NXP_S32_IMCR_SSS_MASK BIT_MASK(4)
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#define NXP_S32_IMCR_IDX_SHIFT 7U
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#define NXP_S32_IMCR_IDX_MASK BIT_MASK(9)
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#define NXP_S32_MSCR_IDX_SHIFT 16U
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#define NXP_S32_MSCR_IDX_MASK BIT_MASK(9)
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#define NXP_S32_MSCR_SIUL2_IDX_SHIFT 25U
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#define NXP_S32_MSCR_SIUL2_IDX_MASK BIT_MASK(3)
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#define NXP_S32_IMCR_SIUL2_IDX_SHIFT 28U
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#define NXP_S32_IMCR_SIUL2_IDX_MASK BIT_MASK(3)
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#define NXP_S32_PINMUX_MSCR_SSS(cfg) \
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(((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
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#define NXP_S32_PINMUX_IMCR_SSS(cfg) \
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(((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
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#define NXP_S32_PINMUX_IMCR_IDX(cfg) \
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(((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
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#define NXP_S32_PINMUX_MSCR_IDX(cfg) \
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(((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
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#define NXP_S32_PINMUX_MSCR_SIUL2_IDX(cfg) \
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(((cfg) & NXP_S32_MSCR_SIUL2_IDX_MASK) << NXP_S32_MSCR_SIUL2_IDX_SHIFT)
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#define NXP_S32_PINMUX_IMCR_SIUL2_IDX(cfg) \
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(((cfg) & NXP_S32_IMCR_SIUL2_IDX_MASK) << NXP_S32_IMCR_SIUL2_IDX_SHIFT)
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#define NXP_S32_PINMUX_GET_MSCR_SSS(cfg) \
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(((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK)
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#define NXP_S32_PINMUX_GET_IMCR_SSS(cfg) \
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(((cfg) >> NXP_S32_IMCR_SSS_SHIFT) & NXP_S32_IMCR_SSS_MASK)
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#define NXP_S32_PINMUX_GET_IMCR_IDX(cfg) \
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(((cfg) >> NXP_S32_IMCR_IDX_SHIFT) & NXP_S32_IMCR_IDX_MASK)
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#define NXP_S32_PINMUX_GET_MSCR_IDX(cfg) \
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(((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK)
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#define NXP_S32_PINMUX_GET_MSCR_SIUL2_IDX(cfg) \
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(((cfg) >> NXP_S32_MSCR_SIUL2_IDX_SHIFT) & NXP_S32_MSCR_SIUL2_IDX_MASK)
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#define NXP_S32_PINMUX_GET_IMCR_SIUL2_IDX(cfg) \
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(((cfg) >> NXP_S32_IMCR_SIUL2_IDX_SHIFT) & NXP_S32_IMCR_SIUL2_IDX_MASK)
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#define NXP_S32_PINMUX(mscr_siul2_idx, imcr_siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \
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(NXP_S32_PINMUX_MSCR_SIUL2_IDX(mscr_siul2_idx) | \
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NXP_S32_PINMUX_IMCR_SIUL2_IDX(imcr_siul2_idx) | \
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NXP_S32_PINMUX_MSCR_IDX(mscr_idx) | \
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NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | \
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NXP_S32_PINMUX_IMCR_IDX(imcr_idx) | \
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NXP_S32_PINMUX_IMCR_SSS(imcr_sss))
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */
dt-util.h
zephyr
dt-bindings
pinctrl
nxp-s32-pinctrl.h
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