Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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nrf-pinctrl.h
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/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
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/*
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* The whole nRF pin configuration information is encoded in a 32-bit bitfield
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* organized as follows:
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*
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* - 31..24: Pin function.
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* - 19-23: Reserved.
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* - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
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* - 17: Clockpin enable.
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* - 16: Pin inversion mode.
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* - 15: Pin low power mode.
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* - 14..11: Pin output drive configuration.
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* - 10..9: Pin pull configuration.
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* - 8..0: Pin number (combination of port and pin).
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*/
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#define NRF_FUN_POS 24U
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#define NRF_FUN_MSK 0xFFU
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#define NRF_GPD_FAST_ACTIVE1_POS 18U
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#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U
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#define NRF_CLOCKPIN_ENABLE_POS 17U
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#define NRF_CLOCKPIN_ENABLE_MSK 0x1U
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#define NRF_INVERT_POS 16U
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#define NRF_INVERT_MSK 0x1U
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#define NRF_LP_POS 15U
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#define NRF_LP_MSK 0x1U
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#define NRF_DRIVE_POS 11U
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#define NRF_DRIVE_MSK 0xFU
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#define NRF_PULL_POS 9U
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#define NRF_PULL_MSK 0x3U
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#define NRF_PIN_POS 0U
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#define NRF_PIN_MSK 0x1FFU
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#define NRF_FUN_UART_TX 0U
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#define NRF_FUN_UART_RX 1U
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#define NRF_FUN_UART_RTS 2U
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#define NRF_FUN_UART_CTS 3U
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#define NRF_FUN_SPIM_SCK 4U
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#define NRF_FUN_SPIM_MOSI 5U
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#define NRF_FUN_SPIM_MISO 6U
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#define NRF_FUN_SPIS_SCK 7U
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#define NRF_FUN_SPIS_MOSI 8U
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#define NRF_FUN_SPIS_MISO 9U
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#define NRF_FUN_SPIS_CSN 10U
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#define NRF_FUN_TWIM_SCL 11U
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#define NRF_FUN_TWIM_SDA 12U
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#define NRF_FUN_I2S_SCK_M 13U
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#define NRF_FUN_I2S_SCK_S 14U
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#define NRF_FUN_I2S_LRCK_M 15U
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#define NRF_FUN_I2S_LRCK_S 16U
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#define NRF_FUN_I2S_SDIN 17U
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#define NRF_FUN_I2S_SDOUT 18U
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#define NRF_FUN_I2S_MCK 19U
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#define NRF_FUN_PDM_CLK 20U
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#define NRF_FUN_PDM_DIN 21U
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#define NRF_FUN_PWM_OUT0 22U
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#define NRF_FUN_PWM_OUT1 23U
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#define NRF_FUN_PWM_OUT2 24U
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#define NRF_FUN_PWM_OUT3 25U
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#define NRF_FUN_QDEC_A 26U
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#define NRF_FUN_QDEC_B 27U
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#define NRF_FUN_QDEC_LED 28U
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#define NRF_FUN_QSPI_SCK 29U
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#define NRF_FUN_QSPI_CSN 30U
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#define NRF_FUN_QSPI_IO0 31U
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#define NRF_FUN_QSPI_IO1 32U
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#define NRF_FUN_QSPI_IO2 33U
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#define NRF_FUN_QSPI_IO3 34U
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#define NRF_FUN_EXMIF_CK 35U
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#define NRF_FUN_EXMIF_DQ0 36U
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#define NRF_FUN_EXMIF_DQ1 37U
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#define NRF_FUN_EXMIF_DQ2 38U
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#define NRF_FUN_EXMIF_DQ3 39U
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#define NRF_FUN_EXMIF_DQ4 40U
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#define NRF_FUN_EXMIF_DQ5 41U
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#define NRF_FUN_EXMIF_DQ6 42U
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#define NRF_FUN_EXMIF_DQ7 43U
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#define NRF_FUN_EXMIF_CS0 44U
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#define NRF_FUN_EXMIF_CS1 45U
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#define NRF_FUN_CAN_TX 46U
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#define NRF_FUN_CAN_RX 47U
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#define NRF_DRIVE_S0S1 0U
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#define NRF_DRIVE_H0S1 1U
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#define NRF_DRIVE_S0H1 2U
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#define NRF_DRIVE_H0H1 3U
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#define NRF_DRIVE_D0S1 4U
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#define NRF_DRIVE_D0H1 5U
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#define NRF_DRIVE_S0D1 6U
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#define NRF_DRIVE_H0D1 7U
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#define NRF_DRIVE_E0E1 8U
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#define NRF_PULL_NONE 0U
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#define NRF_PULL_DOWN 1U
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#define NRF_PULL_UP 3U
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#define NRF_LP_DISABLE 0U
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#define NRF_LP_ENABLE 1U
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#define NRF_PIN_DISCONNECTED NRF_PIN_MSK
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#define NRF_PSEL(fun, port, pin) \
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((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) | \
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((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
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#define NRF_PSEL_DISCONNECTED(fun) \
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(NRF_PIN_DISCONNECTED | \
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((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */
zephyr
dt-bindings
pinctrl
nrf-pinctrl.h
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