memc_nxp_semc.h

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/*
 * Copyright 2026 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DRIVERS_MEMC_NXP_SEMC_H_
#define ZEPHYR_INCLUDE_DRIVERS_MEMC_NXP_SEMC_H_
 
#include <zephyr/device.h>
#include <fsl_semc.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/*
 * The SEMC controller can drive several memory types (SDRAM, SRAM/PSRAM,
 * NOR and NAND) on independent chip-selects. The memc driver only owns the
 * controller: memc_nxp_semc_reconfigure()/memc_nxp_semc_soft_reset()
 * initialize the SEMC core block itself, and the memc_nxp_semc_configure_*()
 * calls program the controller interface for one memory type per chip-select.
 *
 * After SEMC_Init()/reconfigure() no external device is configured yet; a
 * configure_*() call is required before the corresponding memory region can
 * be accessed.
 *
 * NOR/NAND configuration below only sets up the controller side of the
 * interface. Actual flash operations (read/write/erase) are meant to be
 * implemented by flash drivers on top of the SEMC IP-command path, e.g. via
 * SEMC_SendIPCommand()/SEMC_IPCommandNorRead()/SEMC_IPCommandNorWrite() and
 * the NAND equivalents.
 *
 * All functions here are synchronous and block until the operation completes
 * (they serialize access to the controller with a mutex).
 */

int memc_nxp_semc_get_default_config(semc_config_t *config);

int memc_nxp_semc_reconfigure(const struct device *dev, const semc_config_t *config);

int memc_nxp_semc_soft_reset(const struct device *dev);

int memc_nxp_semc_configure_sdram(const struct device *dev, semc_sdram_cs_t cs,
                                   semc_sdram_config_t *config, uint32_t clk_src_hz);

int memc_nxp_semc_configure_sram(const struct device *dev, semc_sram_cs_t cs,
                                  semc_sram_config_t *config, uint32_t clk_src_hz);

int memc_nxp_semc_configure_nor(const struct device *dev, semc_nor_config_t *config,
                                 uint32_t clk_src_hz);

int memc_nxp_semc_configure_nand(const struct device *dev, semc_nand_config_t *config,
                                  uint32_t clk_src_hz);
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_DRIVERS_MEMC_NXP_SEMC_H_ */