Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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mchp-xec-ecia.h
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1/*
2 * Copyright (c) 2021 Microchip Technology
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef __DT_BINDING_MCHP_XEC_ECIA_H
7#define __DT_BINDING_MCHP_XEC_ECIA_H
8
9/*
10 * Encode peripheral interrupt information into a 32-bit unsigned.
11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
15 * connection nd = na.
16 * NOTE: GIRQ22 is a peripheral clock wake only. GIRQ22 and its sources
17 * are not connected to the NVIC. Use 255 for na and nd.
18 */
19#define MCHP_XEC_ECIA(g, gb, na, nd) \
20 (((g) & 0x1f) + (((gb) & 0x1f) << 8) + (((na) & 0xff) << 16) + \
21 (((nd) & 0xff) << 24))
22
23/* extract specific information from encoded MCHP_XEC_ECIA */
24#define MCHP_XEC_ECIA_GIRQ(e) ((e) & 0x1f)
25#define MCHP_XEC_ECIA_GIRQ_POS(e) (((e) >> 8) & 0x1f)
26#define MCHP_XEC_ECIA_NVIC_AGGR(e) (((e) >> 16) & 0xff)
27#define MCHP_XEC_ECIA_NVIC_DIRECT(e) (((e) >> 24) & 0xff)
28
29#endif /* __DT_BINDING_MCHP_XEC_ECIA_H */