Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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lpc11u6x-pinctrl.h
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1/*
2 * Copyright (c) 2020 Seagate Technology LLC
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_
9
52#define IOCON_FUNC0 0
53#define IOCON_FUNC1 1
54#define IOCON_FUNC2 2
55#define IOCON_FUNC3 3
56#define IOCON_FUNC4 4
57#define IOCON_FUNC5 5
58
59#define IOCON_MODE_INACT (0 << 3) /* No pull resistor. */
60#define IOCON_MODE_PULLDOWN (1 << 3) /* Enable pull-down resistor. */
61#define IOCON_MODE_PULLUP (2 << 3) /* Enable Pull-up resistor. */
62#define IOCON_MODE_REPEATER (3 << 3) /* Repeater mode. */
63
64#define IOCON_HYS_EN (1 << 5) /* Enable hysteresis. */
65
66#define IOCON_INV_EN (1 << 6) /* Invert input polarity. */
67
68/* Only for analog pins. */
69#define IOCON_ADMODE_EN (0 << 7) /* Enable analog input mode. */
70#define IOCON_DIGMODE_EN (1 << 7) /* Enable digital I/O mode. */
71#define IOCON_FILTR_DIS (1 << 8) /* Disable noise filtering. */
72
73/* Only for open-drain pins (I2C). */
74#define IOCON_SFI2C_EN (0 << 8) /* I2C standard mode / Fast-mode. */
75#define IOCON_STDI2C_EN (1 << 8) /* GPIO functionality. */
76#define IOCON_FASTI2C_EN (2 << 8) /* I2C Fast-mode Plus. */
77
78#define IOCON_OPENDRAIN_EN (1 << 10) /* Enable open-drain mode. */
79
80/*
81 * The digital filter mode allows to discard input pulses shorter than
82 * 1, 2 or 3 clock cycles.
83 */
84#define IOCON_S_MODE_0CLK (0 << 11) /* No input filter. */
85#define IOCON_S_MODE_1CLK (1 << 11)
86#define IOCON_S_MODE_2CLK (2 << 11)
87#define IOCON_S_MODE_3CLK (3 << 11)
88
89/*
90 * Clock divisor.
91 */
92#define IOCON_CLKDIV0 (0 << 13)
93#define IOCON_CLKDIV1 (1 << 13)
94#define IOCON_CLKDIV2 (2 << 13)
95#define IOCON_CLKDIV3 (3 << 13)
96#define IOCON_CLKDIV4 (4 << 13)
97#define IOCON_CLKDIV5 (5 << 13)
98#define IOCON_CLKDIV6 (6 << 13)
99
100
101/*
102 * Pin control definitions used by LPC pin control driver to make pinmux
103 * selections.
104 */
105
106#define IOCON_MUX(offset, type, mux) \
107 (((offset & 0xFFF) << 20) | \
108 (((type) & 0x3) << 18) | \
109 (((mux) & 0xF) << 0))
110
111#define IOCON_TYPE_D 0x0
112#define IOCON_TYPE_I 0x1
113#define IOCON_TYPE_A 0x2
114
115#define RESET_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */
116#define PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */
117#define PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
118#define CLKOUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */
119#define CT32B0_MAT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */
120#define USB_FTOGGLE_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
121#define PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
122#define SSP0_SSEL_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */
123#define CT16B0_CAP0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
124#define R_0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */
125#define PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
126#define USB_VBUS_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */
127#define R_1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */
128#define PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_I, 0) /* PIO0_4 */
129#define I2C0_SCL_PIO0_4 IOCON_MUX(4, IOCON_TYPE_I, 1) /* PIO0_4 */
130#define R_2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_I, 2) /* PIO0_4 */
131#define PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_I, 0) /* PIO0_5 */
132#define I2C0_SDA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_I, 1) /* PIO0_5 */
133#define R_3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_I, 2) /* PIO0_5 */
134#define PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
135#define R_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */
136#define SSP0_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
137#define R_4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */
138#define PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */
139#define U0_CTS_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */
140#define R_5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */
141#define I2C1_SCL_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */
142#define PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
143#define SSP0_MISO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */
144#define CT16B0_MAT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */
145#define R_6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */
146#define PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */
147#define SSP0_MOSI_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */
148#define CT16B0_MAT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */
149#define R_7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */
150#define SWCLK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
151#define PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */
152#define SSP0_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
153#define CT16B0_MAT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */
154#define TDI_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */
155#define PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */
156#define ADC_9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */
157#define CT32B0_MAT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */
158#define U1_RTS_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 4) /* PIO0_11 */
159#define U1_SCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 5) /* PIO0_11 */
160#define TMS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */
161#define PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */
162#define ADC_8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */
163#define CT32B1_CAP0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */
164#define U1_CTS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */
165#define PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */
166#define TDO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 0) /* PIO0_13 */
167#define PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 1) /* PIO0_13 */
168#define ADC_7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 2) /* PIO0_13 */
169#define CT32B1_MAT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 3) /* PIO0_13 */
170#define U1_RXD_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 4) /* PIO0_13 */
171#define PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_A, 5) /* PIO0_13 */
172#define TRST_PIO0_14 IOCON_MUX(14, IOCON_TYPE_A, 0) /* PIO0_14 */
173#define PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_A, 1) /* PIO0_14 */
174#define ADC_6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_A, 2) /* PIO0_14 */
175#define CT32B1_MAT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_A, 3) /* PIO0_14 */
176#define U1_TXD_PIO0_14 IOCON_MUX(14, IOCON_TYPE_A, 4) /* PIO0_14 */
177#define SWDIO_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */
178#define PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */
179#define ADC_3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */
180#define CT32B1_MAT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */
181#define WAKEUP_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */
182#define PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */
183#define ADC_2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */
184#define CT32B1_MAT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */
185#define R_8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 4) /* PIO0_16 */
186#define PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */
187#define U0_RTS_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */
188#define CT32B0_CAP0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */
189#define U0_SCLK_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */
190#define PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */
191#define U0_RXD_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */
192#define CT32B0_MAT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */
193#define PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
194#define U0_TXD_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */
195#define CT32B0_MAT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */
196#define PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
197#define CT16B1_CAP0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */
198#define U2_RXD_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */
199#define PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
200#define CT16B1_MAT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */
201#define SSP1_MOSI_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */
202#define PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_A, 0) /* PIO0_22 */
203#define ADC_11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_A, 1) /* PIO0_22 */
204#define CT16B1_CAP1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_A, 2) /* PIO0_22 */
205#define SSP1_MISO_PIO0_22 IOCON_MUX(22, IOCON_TYPE_A, 3) /* PIO0_22 */
206#define PIO0_23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
207#define ADC_1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */
208#define R_9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */
209#define U0_RI_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */
210#define SSP1_SSEL_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */
211#define PIO1_0_PIO1_0 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO1_0 */
212#define CT32B1_MAT0_PIO1_0 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO1_0 */
213#define R_10_PIO1_0 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO1_0 */
214#define U2_TXD_PIO1_0 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO1_0 */
215#define PIO1_1_PIO1_1 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO1_1 */
216#define CT32B1_MAT1_PIO1_1 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO1_1 */
217#define R_11_PIO1_1 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO1_1 */
218#define U0_DTR_PIO1_1 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO1_1 */
219#define PIO1_2_PIO1_2 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO1_2 */
220#define CT32B1_MAT2_PIO1_2 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO1_2 */
221#define R_12_PIO1_2 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO1_2 */
222#define U1_RXD_PIO1_2 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO1_2 */
223#define PIO1_3_PIO1_3 IOCON_MUX(27, IOCON_TYPE_A, 0) /* PIO1_3 */
224#define CT32B1_MAT3_PIO1_3 IOCON_MUX(27, IOCON_TYPE_A, 1) /* PIO1_3 */
225#define R_13_PIO1_3 IOCON_MUX(27, IOCON_TYPE_A, 2) /* PIO1_3 */
226#define I2C1_SDA_PIO1_3 IOCON_MUX(27, IOCON_TYPE_A, 3) /* PIO1_3 */
227#define ADC_5_PIO1_3 IOCON_MUX(27, IOCON_TYPE_A, 4) /* PIO1_3 */
228#define PIO1_4_PIO1_4 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO1_4 */
229#define CT32B1_CAP0_PIO1_4 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO1_4 */
230#define R_14_PIO1_4 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO1_4 */
231#define U0_DSR_PIO1_4 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO1_4 */
232#define PIO1_5_PIO1_5 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO1_5 */
233#define CT32B1_CAP1_PIO1_5 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO1_5 */
234#define R_15_PIO1_5 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO1_5 */
235#define U0_DCD_PIO1_5 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO1_5 */
236#define PIO1_6_PIO1_6 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO1_6 */
237#define R_16_PIO1_6 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO1_6 */
238#define U2_RXD_PIO1_6 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO1_6 */
239#define CT32B0_CAP1_PIO1_6 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO1_6 */
240#define PIO1_7_PIO1_7 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO1_7 */
241#define R_17_PIO1_7 IOCON_MUX(31, IOCON_TYPE_D, 1) /* PIO1_7 */
242#define U2_CTS_PIO1_7 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO1_7 */
243#define CT16B1_CAP0_PIO1_7 IOCON_MUX(31, IOCON_TYPE_D, 3) /* PIO1_7 */
244#define PIO1_8_PIO1_8 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_8 */
245#define R_18_PIO1_8 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_8 */
246#define U1_TXD_PIO1_8 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_8 */
247#define CT16B0_CAP0_PIO1_8 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_8 */
248#define PIO1_9_PIO1_9 IOCON_MUX(33, IOCON_TYPE_A, 0) /* PIO1_9 */
249#define U0_CTS_PIO1_9 IOCON_MUX(33, IOCON_TYPE_A, 1) /* PIO1_9 */
250#define CT16B1_MAT1_PIO1_9 IOCON_MUX(33, IOCON_TYPE_A, 2) /* PIO1_9 */
251#define ADC_0_PIO1_9 IOCON_MUX(33, IOCON_TYPE_A, 3) /* PIO1_9 */
252#define PIO1_10_PIO1_10 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_10 */
253#define U2_RTS_PIO1_10 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_10 */
254#define U2_SCLK_PIO1_10 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_10 */
255#define CT16B1_MAT0_PIO1_10 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_10 */
256#define PIO1_11_PIO1_11 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_11 */
257#define I2C1_SCL_PIO1_11 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_11 */
258#define CT16B0_MAT2_PIO1_11 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_11 */
259#define U0_RI_PIO1_11 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_11 */
260#define PIO1_12_PIO1_12 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_12 */
261#define SSP0_MOSI_PIO1_12 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_12 */
262#define CT16B0_MAT1_PIO1_12 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_12 */
263#define R_21_PIO1_12 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_12 */
264#define PIO1_13_PIO1_13 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_13 */
265#define U1_CTS_PIO1_13 IOCON_MUX(37, IOCON_TYPE_D, 1) /* PIO1_13 */
266#define SCT0_OUT3_PIO1_13 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_13 */
267#define R_22_PIO1_13 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_13 */
268#define PIO1_14_PIO1_14 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_14 */
269#define I2C1_SDA_PIO1_14 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_14 */
270#define CT32B1_MAT2_PIO1_14 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_14 */
271#define R_23_PIO1_14 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_14 */
272#define PIO1_15_PIO1_15 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_15 */
273#define SSP0_SSEL_PIO1_15 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_15 */
274#define CT32B1_MAT3_PIO1_15 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_15 */
275#define R_24_PIO1_15 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_15 */
276#define PIO1_16_PIO1_16 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_16 */
277#define SSP0_MISO_PIO1_16 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_16 */
278#define CT16B0_MAT0_PIO1_16 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_16 */
279#define R_25_PIO1_16 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_16 */
280#define PIO1_17_PIO1_17 IOCON_MUX(41, IOCON_TYPE_D, 0) /* PIO1_17 */
281#define CT16B0_CAP2_PIO1_17 IOCON_MUX(41, IOCON_TYPE_D, 1) /* PIO1_17 */
282#define U0_RXD_PIO1_17 IOCON_MUX(41, IOCON_TYPE_D, 2) /* PIO1_17 */
283#define R_26_PIO1_17 IOCON_MUX(41, IOCON_TYPE_D, 3) /* PIO1_17 */
284#define PIO1_18_PIO1_18 IOCON_MUX(42, IOCON_TYPE_D, 0) /* PIO1_18 */
285#define CT16B1_CAP1_PIO1_18 IOCON_MUX(42, IOCON_TYPE_D, 1) /* PIO1_18 */
286#define U0_TXD_PIO1_18 IOCON_MUX(42, IOCON_TYPE_D, 2) /* PIO1_18 */
287#define R_27_PIO1_18 IOCON_MUX(42, IOCON_TYPE_D, 3) /* PIO1_18 */
288#define PIO1_19_PIO1_19 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_19 */
289#define U2_CTS_PIO1_19 IOCON_MUX(43, IOCON_TYPE_D, 1) /* PIO1_19 */
290#define SCT0_OUT0_PIO1_19 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_19 */
291#define R_28_PIO1_19 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_19 */
292#define PIO1_20_PIO1_20 IOCON_MUX(44, IOCON_TYPE_D, 0) /* PIO1_20 */
293#define U0_DSR_PIO1_20 IOCON_MUX(44, IOCON_TYPE_D, 1) /* PIO1_20 */
294#define SSP1_SCK_PIO1_20 IOCON_MUX(44, IOCON_TYPE_D, 2) /* PIO1_20 */
295#define CT16B0_MAT0_PIO1_20 IOCON_MUX(44, IOCON_TYPE_D, 3) /* PIO1_20 */
296#define PIO1_21_PIO1_21 IOCON_MUX(45, IOCON_TYPE_D, 0) /* PIO1_21 */
297#define U0_DCD_PIO1_21 IOCON_MUX(45, IOCON_TYPE_D, 1) /* PIO1_21 */
298#define SSP1_MISO_PIO1_21 IOCON_MUX(45, IOCON_TYPE_D, 2) /* PIO1_21 */
299#define CT16B0_CAP1_PIO1_21 IOCON_MUX(45, IOCON_TYPE_D, 3) /* PIO1_21 */
300#define PIO1_22_PIO1_22 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_22 */
301#define SSP1_MOSI_PIO1_22 IOCON_MUX(46, IOCON_TYPE_A, 1) /* PIO1_22 */
302#define CT32B1_CAP1_PIO1_22 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_22 */
303#define ADC_4_PIO1_22 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_22 */
304#define R_29_PIO1_22 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_22 */
305#define PIO1_23_PIO1_23 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_23 */
306#define CT16B1_MAT1_PIO1_23 IOCON_MUX(47, IOCON_TYPE_D, 1) /* PIO1_23 */
307#define SSP1_SSEL_PIO1_23 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_23 */
308#define U2_TXD_PIO1_23 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_23 */
309#define PIO1_24_PIO1_24 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_24 */
310#define CT32B0_MAT0_PIO1_24 IOCON_MUX(48, IOCON_TYPE_D, 1) /* PIO1_24 */
311#define I2C1_SDA_PIO1_24 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_24 */
312#define PIO1_25_PIO1_25 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_25 */
313#define U2_RTS_PIO1_25 IOCON_MUX(49, IOCON_TYPE_D, 1) /* PIO1_25 */
314#define U2_SCLK_PIO1_25 IOCON_MUX(49, IOCON_TYPE_D, 2) /* PIO1_25 */
315#define SCT0_IN0_PIO1_25 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_25 */
316#define R_30_PIO1_25 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_25 */
317#define PIO1_26_PIO1_26 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_26 */
318#define CT32B0_MAT2_PIO1_26 IOCON_MUX(50, IOCON_TYPE_D, 1) /* PIO1_26 */
319#define U0_RXD_PIO1_26 IOCON_MUX(50, IOCON_TYPE_D, 2) /* PIO1_26 */
320#define R_19_PIO1_26 IOCON_MUX(50, IOCON_TYPE_D, 3) /* PIO1_26 */
321#define PIO1_27_PIO1_27 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_27 */
322#define CT32B0_MAT3_PIO1_27 IOCON_MUX(51, IOCON_TYPE_D, 1) /* PIO1_27 */
323#define U0_TXD_PIO1_27 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_27 */
324#define R_20_PIO1_27 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_27 */
325#define SSP1_SCK_PIO1_27 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_27 */
326#define PIO1_28_PIO1_28 IOCON_MUX(52, IOCON_TYPE_D, 0) /* PIO1_28 */
327#define CT32B0_CAP0_PIO1_28 IOCON_MUX(52, IOCON_TYPE_D, 1) /* PIO1_28 */
328#define U0_SCLK_PIO1_28 IOCON_MUX(52, IOCON_TYPE_D, 2) /* PIO1_28 */
329#define U0_RTS_PIO1_28 IOCON_MUX(52, IOCON_TYPE_D, 3) /* PIO1_28 */
330#define PIO1_29_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 0) /* PIO1_29 */
331#define SSP0_SCK_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 1) /* PIO1_29 */
332#define CT32B0_CAP1_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 2) /* PIO1_29 */
333#define U0_DTRn_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 3) /* PIO1_29 */
334#define ADC_10_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 4) /* PIO1_29 */
335#define PIO1_30_PIO1_30 IOCON_MUX(54, IOCON_TYPE_D, 0) /* PIO1_30 */
336#define I2C1_SCL_PIO1_30 IOCON_MUX(54, IOCON_TYPE_D, 1) /* PIO1_30 */
337#define SCT0_IN3_PIO1_30 IOCON_MUX(54, IOCON_TYPE_D, 2) /* PIO1_30 */
338#define R_31_PIO1_30 IOCON_MUX(54, IOCON_TYPE_D, 3) /* PIO1_30 */
339#define PIO1_31_PIO1_31 IOCON_MUX(55, IOCON_TYPE_D, 0) /* PIO1_31 */
340#define PIO2_0_PIO2_0 IOCON_MUX(60, IOCON_TYPE_A, 0) /* PIO2_0 */
341#define XTALIN_PIO2_0 IOCON_MUX(60, IOCON_TYPE_A, 1) /* PIO2_0 */
342#define PIO2_1_PIO2_1 IOCON_MUX(61, IOCON_TYPE_A, 0) /* PIO2_1 */
343#define XTALOUT_PIO2_1 IOCON_MUX(61, IOCON_TYPE_A, 1) /* PIO2_1 */
344#define PIO2_2_PIO2_2 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO2_2 */
345#define U3_RTS_PIO2_2 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO2_2 */
346#define U3_SCLK_PIO2_2 IOCON_MUX(63, IOCON_TYPE_D, 2) /* PIO2_2 */
347#define SCT0_OUT1_PIO2_2 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO2_2 */
348#define PIO2_3_PIO2_3 IOCON_MUX(64, IOCON_TYPE_D, 0) /* PIO2_3 */
349#define U3_RXD_PIO2_3 IOCON_MUX(64, IOCON_TYPE_D, 1) /* PIO2_3 */
350#define CT32B0_MAT1_PIO2_3 IOCON_MUX(64, IOCON_TYPE_D, 2) /* PIO2_3 */
351#define PIO2_4_PIO2_4 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_4 */
352#define U3_TXD_PIO2_4 IOCON_MUX(65, IOCON_TYPE_D, 1) /* PIO2_4 */
353#define CT32B0_MAT2_PIO2_4 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_4 */
354#define PIO2_5_PIO2_5 IOCON_MUX(66, IOCON_TYPE_D, 0) /* PIO2_5 */
355#define U3_CTS_PIO2_5 IOCON_MUX(66, IOCON_TYPE_D, 1) /* PIO2_5 */
356#define SCT0_IN1_PIO2_5 IOCON_MUX(66, IOCON_TYPE_D, 2) /* PIO2_5 */
357#define PIO2_6_PIO2_6 IOCON_MUX(67, IOCON_TYPE_D, 0) /* PIO2_6 */
358#define U1_RTS_PIO2_6 IOCON_MUX(67, IOCON_TYPE_D, 1) /* PIO2_6 */
359#define U1_SCLK_PIO2_6 IOCON_MUX(67, IOCON_TYPE_D, 2) /* PIO2_6 */
360#define SCT0_IN2_PIO2_6 IOCON_MUX(67, IOCON_TYPE_D, 3) /* PIO2_6 */
361#define PIO2_7_PIO2_7 IOCON_MUX(68, IOCON_TYPE_D, 0) /* PIO2_7 */
362#define SSP0_SCK_PIO2_7 IOCON_MUX(68, IOCON_TYPE_D, 1) /* PIO2_7 */
363#define SCT0_OUT2_PIO2_7 IOCON_MUX(68, IOCON_TYPE_D, 2) /* PIO2_7 */
364#define PIO2_8_PIO2_8 IOCON_MUX(69, IOCON_TYPE_D, 0) /* PIO2_8 */
365#define SCT1_IN0_PIO2_8 IOCON_MUX(69, IOCON_TYPE_D, 1) /* PIO2_8 */
366#define PIO2_9_PIO2_9 IOCON_MUX(70, IOCON_TYPE_D, 0) /* PIO2_9 */
367#define SCT1_IN1_PIO2_9 IOCON_MUX(70, IOCON_TYPE_D, 1) /* PIO2_9 */
368#define PIO2_10_PIO2_10 IOCON_MUX(71, IOCON_TYPE_D, 0) /* PIO2_10 */
369#define U4_RTS_PIO2_10 IOCON_MUX(71, IOCON_TYPE_D, 1) /* PIO2_10 */
370#define U4_SCLK_PIO2_10 IOCON_MUX(71, IOCON_TYPE_D, 2) /* PIO2_10 */
371#define PIO2_11_PIO2_11 IOCON_MUX(72, IOCON_TYPE_D, 0) /* PIO2_11 */
372#define U4_RXD_PIO2_11 IOCON_MUX(72, IOCON_TYPE_D, 1) /* PIO2_11 */
373#define PIO2_12_PIO2_12 IOCON_MUX(73, IOCON_TYPE_D, 0) /* PIO2_12 */
374#define U4_TXD_PIO2_12 IOCON_MUX(73, IOCON_TYPE_D, 1) /* PIO2_12 */
375#define PIO2_13_PIO2_13 IOCON_MUX(74, IOCON_TYPE_D, 0) /* PIO2_13 */
376#define U4_CTS_PIO2_13 IOCON_MUX(74, IOCON_TYPE_D, 1) /* PIO2_13 */
377#define PIO2_14_PIO2_14 IOCON_MUX(75, IOCON_TYPE_D, 0) /* PIO2_14 */
378#define SCT1_IN2_PIO2_14 IOCON_MUX(75, IOCON_TYPE_D, 1) /* PIO2_14 */
379#define PIO2_15_PIO2_15 IOCON_MUX(76, IOCON_TYPE_D, 0) /* PIO2_15 */
380#define SCT1_IN3_PIO2_15 IOCON_MUX(76, IOCON_TYPE_D, 1) /* PIO2_15 */
381#define PIO2_16_PIO2_16 IOCON_MUX(77, IOCON_TYPE_D, 0) /* PIO2_16 */
382#define SCT1_OUT0_PIO2_16 IOCON_MUX(77, IOCON_TYPE_D, 1) /* PIO2_16 */
383#define PIO2_17_PIO2_17 IOCON_MUX(78, IOCON_TYPE_D, 0) /* PIO2_17 */
384#define SCT1_OUT1_PIO2_17 IOCON_MUX(78, IOCON_TYPE_D, 1) /* PIO2_17 */
385#define PIO2_18_PIO2_18 IOCON_MUX(79, IOCON_TYPE_D, 0) /* PIO2_18 */
386#define SCT1_OUT2_PIO2_18 IOCON_MUX(79, IOCON_TYPE_D, 1) /* PIO2_18 */
387#define PIO2_19_PIO2_19 IOCON_MUX(80, IOCON_TYPE_D, 0) /* PIO2_19 */
388#define SCT1_OUT3_PIO2_19 IOCON_MUX(80, IOCON_TYPE_D, 1) /* PIO2_19 */
389#define PIO2_20_PIO2_20 IOCON_MUX(81, IOCON_TYPE_D, 0) /* PIO2_20 */
390#define PIO2_21_PIO2_21 IOCON_MUX(82, IOCON_TYPE_D, 0) /* PIO2_21 */
391#define PIO2_22_PIO2_22 IOCON_MUX(83, IOCON_TYPE_D, 0) /* PIO2_22 */
392#define PIO2_23_PIO2_23 IOCON_MUX(84, IOCON_TYPE_D, 0) /* PIO2_23 */
393
394#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_ */