Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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intel_socfpga_reset.h
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1/*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2023, Intel Corporation
5 *
6 */
7
8#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
9#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
10
11/* The Reset line value will be used by the reset controller driver to
12 * derive the register offset and the associated device bit to perform
13 * device assert and de-assert.
14 *
15 * The reset lines should be passed as a parameter to the resets property
16 * of the driver node in dtsi which will call reset-controller driver to
17 * assert/de-assert itself.
18 *
19 * Example: Deriving Reset Line value
20 * per0modrst register offset = 0x24;
21 * NAND RSTLINE pin = 5;
22 * RSTMGR_NAND_RSTLINE = (0x24 * 8) + 5 = 293
23 */
24
25#define RSTMGR_SDMCOLDRST_RSTLINE 0
26#define RSTMGR_SDMWARMRST_RSTLINE 1
27#define RSTMGR_SDMLASTPORRST_RSTLINE 2
28#define RSTMGR_L4WD0RST_RSTLINE 16
29#define RSTMGR_L4WD1RST_RSTLINE 17
30#define RSTMGR_L4WD2RST_RSTLINE 18
31#define RSTMGR_L4WD3RST_RSTLINE 19
32#define RSTMGR_L4WD4RST_RSTLINE 20
33#define RSTMGR_DEBUGRST_RSTLINE 21
34#define RSTMGR_CSDAPRST_RSTLINE 22
35#define RSTMGR_EMIFTIMEOUT_RSTLINE 64
36#define RSTMGR_FPGAHSTIMEOUT_RSTLINE 66
37#define RSTMGR_ETRSTALLTIMEOUT_RSTLINE 67
38#define RSTMGR_LWSOC2FPGATIMEOUT_RSTLINE 72
39#define RSTMGR_SOC2FPGATIMEOUT_RSTLINE 73
40#define RSTMGR_F2SDRAMTIMEOUT_RSTLINE 74
41#define RSTMGR_F2STIMEOUT_RSTLINE 75
42#define RSTMGR_L3NOCDBGTIMEOUT_RSTLINE 79
43#define RSTMGR_DEBUGL3NOCTIMEOUT_RSTLINE 80
44#define RSTMGR_EMIF_FLUSH_RSTLINE 128
45#define RSTMGR_FPGAHSEN_RSTLINE 130
46#define RSTMGR_ETRSTALLEN_RSTLINE 131
47#define RSTMGR_LWSOC2FPGA_FLUSH_RSTLINE 137
48#define RSTMGR_SOC2FPGA_FLUSH_RSTLINE 138
49#define RSTMGR_F2SDRAM_FLUSH_RSTLINE 139
50#define RSTMGR_F2SOC_FLUSH_RSTLINE 140
51#define RSTMGR_L3NOC_DBG_RSTLINE 144
52#define RSTMGR_DEBUG_L3NOC_RSTLINE 145
53#define RSTMGR_EMIF_FLUSH_REQ_RSTLINE 160
54#define RSTMGR_FPGAHSREQ_RSTLINE 162
55#define RSTMGR_ETRSTALLREQ_RSTLINE 163
56#define RSTMGR_LWSOC2FPGA_FLUSH_REQ_RSTLINE 169
57#define RSTMGR_SOC2FPGA_FLUSH_REQ_RSTLINE 170
58#define RSTMGR_F2SDRAM_FLUSH_REQ_RSTLINE 171
59#define RSTMGR_F2S_FLUSH_REQ_RSTLINE 172
60#define RSTMGR_L3NOC_DBG_REQ_RSTLINE 176
61#define RSTMGR_DEBUG_L3NOC_REQ_RSTLINE 177
62#define RSTMGR_EMIF_FLUSH_ACK_RSTLINE 192
63#define RSTMGR_FPGAHSACK_RSTLINE 194
64#define RSTMGR_ETRSTALLACK_RSTLINE 195
65#define RSTMGR_LWSOC2FPGA_FLUSH_ACK_RSTLINE 201
66#define RSTMGR_SOC2FPGA_FLUSH_ACK_RSTLINE 202
67#define RSTMGR_F2SDRAM_FLUSH_ACK_RSTLINE 203
68#define RSTMGR_F2S_FLUSH_ACK_RSTLINE 204
69#define RSTMGR_L3NOC_DBG_ACK_RSTLINE 208
70#define RSTMGR_DEBUG_L3NOC_ACK_RSTLINE 209
71#define RSTMGR_ETRSTALLWARMRST_RSTLINE 224
72#define RSTMGR_TSN0_RSTLINE 288
73#define RSTMGR_TSN1_RSTLINE 289
74#define RSTMGR_TSN2_RSTLINE 290
75#define RSTMGR_USB0_RSTLINE 291
76#define RSTMGR_USB1_RSTLINE 292
77#define RSTMGR_NAND_RSTLINE 293
78#define RSTMGR_SOFTPHY_RSTLINE 294
79#define RSTMGR_SDMMC_RSTLINE 295
80#define RSTMGR_TSN0ECC_RSTLINE 296
81#define RSTMGR_TSN1ECC_RSTLINE 297
82#define RSTMGR_TSN2ECC_RSTLINE 298
83#define RSTMGR_USB0ECC_RSTLINE 299
84#define RSTMGR_USB1ECC_RSTLINE 300
85#define RSTMGR_NANDECC_RSTLINE 301
86#define RSTMGR_SDMMCECC_RSTLINE 303
87#define RSTMGR_DMA_RSTLINE 304
88#define RSTMGR_SPIM0_RSTLINE 305
89#define RSTMGR_SPIM1_RSTLINE 306
90#define RSTMGR_SPIS0_RSTLINE 307
91#define RSTMGR_SPIS1_RSTLINE 308
92#define RSTMGR_DMAECC_RSTLINE 309
93#define RSTMGR_EMACPTP_RSTLINE 310
94#define RSTMGR_DMAIF0_RSTLINE 312
95#define RSTMGR_DMAIF1_RSTLINE 313
96#define RSTMGR_DMAIF2_RSTLINE 314
97#define RSTMGR_DMAIF3_RSTLINE 315
98#define RSTMGR_DMAIF4_RSTLINE 316
99#define RSTMGR_DMAIF5_RSTLINE 317
100#define RSTMGR_DMAIF6_RSTLINE 318
101#define RSTMGR_DMAIF7_RSTLINE 319
102#define RSTMGR_WATCHDOG0_RSTLINE 320
103#define RSTMGR_WATCHDOG1_RSTLINE 321
104#define RSTMGR_WATCHDOG2_RSTLINE 322
105#define RSTMGR_WATCHDOG3_RSTLINE 323
106#define RSTMGR_L4SYSTIMER0_RSTLINE 324
107#define RSTMGR_L4SYSTIMER1_RSTLINE 325
108#define RSTMGR_SPTIMER0_RSTLINE 326
109#define RSTMGR_SPTIMER1_RSTLINE 327
110#define RSTMGR_I2C0_RSTLINE 328
111#define RSTMGR_I2C1_RSTLINE 329
112#define RSTMGR_I2C2_RSTLINE 330
113#define RSTMGR_I2C3_RSTLINE 331
114#define RSTMGR_I2C4_RSTLINE 332
115#define RSTMGR_I3C0_RSTLINE 333
116#define RSTMGR_I3C1_RSTLINE 334
117#define RSTMGR_UART0_RSTLINE 336
118#define RSTMGR_UART1_RSTLINE 337
119#define RSTMGR_GPIO0_RSTLINE 344
120#define RSTMGR_GPIO1_RSTLINE 345
121#define RSTMGR_WATCHDOG4_RSTLINE 346
122#define RSTMGR_SOC2FPGA_RSTLINE 352
123#define RSTMGR_LWSOC2FPGA_RSTLINE 353
124#define RSTMGR_FPGA2SOC_RSTLINE 354
125#define RSTMGR_FPGA2SDRAM_RSTLINE 355
126#define RSTMGR_MPFE_RSTLINE 358
127#define RSTMGR_DBG_RST_RSTLINE 480
128#define RSTMGR_SOC2FPGA_WARM_RSTLINE 608
129#define RSTMGR_LWSOC2FPGA_WARM_RSTLINE 609
130#define RSTMGR_FPGA2SOC_WARM_RSTLINE 610
131#define RSTMGR_FPGA2SDRAM_WARM_RSTLINE 611
132#define RSTMGR_MPFE_WARM_RSTLINE 614
133
134#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_ */