Zephyr API Documentation
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A Scalable Open Source RTOS
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intel_socfpga_reset.h
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2023, Intel Corporation
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*
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
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/* The Reset line value will be used by the reset controller driver to
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* derive the register offset and the associated device bit to perform
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* device assert and de-assert.
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*
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* The reset lines should be passed as a parameter to the resets property
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* of the driver node in dtsi which will call reset-controller driver to
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* assert/de-assert itself.
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*
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* Example: Deriving Reset Line value
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* per0modrst register offset = 0x24;
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* NAND RSTLINE pin = 5;
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* RSTMGR_NAND_RSTLINE = (0x24 * 8) + 5 = 293
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*/
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#define RSTMGR_SDMCOLDRST_RSTLINE 0
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#define RSTMGR_SDMWARMRST_RSTLINE 1
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#define RSTMGR_SDMLASTPORRST_RSTLINE 2
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#define RSTMGR_L4WD0RST_RSTLINE 16
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#define RSTMGR_L4WD1RST_RSTLINE 17
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#define RSTMGR_L4WD2RST_RSTLINE 18
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#define RSTMGR_L4WD3RST_RSTLINE 19
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#define RSTMGR_L4WD4RST_RSTLINE 20
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#define RSTMGR_DEBUGRST_RSTLINE 21
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#define RSTMGR_CSDAPRST_RSTLINE 22
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#define RSTMGR_EMIFTIMEOUT_RSTLINE 64
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#define RSTMGR_FPGAHSTIMEOUT_RSTLINE 66
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#define RSTMGR_ETRSTALLTIMEOUT_RSTLINE 67
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#define RSTMGR_LWSOC2FPGATIMEOUT_RSTLINE 72
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#define RSTMGR_SOC2FPGATIMEOUT_RSTLINE 73
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#define RSTMGR_F2SDRAMTIMEOUT_RSTLINE 74
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#define RSTMGR_F2STIMEOUT_RSTLINE 75
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#define RSTMGR_L3NOCDBGTIMEOUT_RSTLINE 79
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#define RSTMGR_DEBUGL3NOCTIMEOUT_RSTLINE 80
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#define RSTMGR_EMIF_FLUSH_RSTLINE 128
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#define RSTMGR_FPGAHSEN_RSTLINE 130
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#define RSTMGR_ETRSTALLEN_RSTLINE 131
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#define RSTMGR_LWSOC2FPGA_FLUSH_RSTLINE 137
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#define RSTMGR_SOC2FPGA_FLUSH_RSTLINE 138
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#define RSTMGR_F2SDRAM_FLUSH_RSTLINE 139
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#define RSTMGR_F2SOC_FLUSH_RSTLINE 140
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#define RSTMGR_L3NOC_DBG_RSTLINE 144
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#define RSTMGR_DEBUG_L3NOC_RSTLINE 145
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#define RSTMGR_EMIF_FLUSH_REQ_RSTLINE 160
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#define RSTMGR_FPGAHSREQ_RSTLINE 162
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#define RSTMGR_ETRSTALLREQ_RSTLINE 163
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#define RSTMGR_LWSOC2FPGA_FLUSH_REQ_RSTLINE 169
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#define RSTMGR_SOC2FPGA_FLUSH_REQ_RSTLINE 170
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#define RSTMGR_F2SDRAM_FLUSH_REQ_RSTLINE 171
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#define RSTMGR_F2S_FLUSH_REQ_RSTLINE 172
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#define RSTMGR_L3NOC_DBG_REQ_RSTLINE 176
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#define RSTMGR_DEBUG_L3NOC_REQ_RSTLINE 177
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#define RSTMGR_EMIF_FLUSH_ACK_RSTLINE 192
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#define RSTMGR_FPGAHSACK_RSTLINE 194
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#define RSTMGR_ETRSTALLACK_RSTLINE 195
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#define RSTMGR_LWSOC2FPGA_FLUSH_ACK_RSTLINE 201
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#define RSTMGR_SOC2FPGA_FLUSH_ACK_RSTLINE 202
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#define RSTMGR_F2SDRAM_FLUSH_ACK_RSTLINE 203
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#define RSTMGR_F2S_FLUSH_ACK_RSTLINE 204
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#define RSTMGR_L3NOC_DBG_ACK_RSTLINE 208
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#define RSTMGR_DEBUG_L3NOC_ACK_RSTLINE 209
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#define RSTMGR_ETRSTALLWARMRST_RSTLINE 224
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#define RSTMGR_TSN0_RSTLINE 288
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#define RSTMGR_TSN1_RSTLINE 289
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#define RSTMGR_TSN2_RSTLINE 290
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#define RSTMGR_USB0_RSTLINE 291
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#define RSTMGR_USB1_RSTLINE 292
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#define RSTMGR_NAND_RSTLINE 293
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#define RSTMGR_SOFTPHY_RSTLINE 294
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#define RSTMGR_SDMMC_RSTLINE 295
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#define RSTMGR_TSN0ECC_RSTLINE 296
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#define RSTMGR_TSN1ECC_RSTLINE 297
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#define RSTMGR_TSN2ECC_RSTLINE 298
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#define RSTMGR_USB0ECC_RSTLINE 299
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#define RSTMGR_USB1ECC_RSTLINE 300
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#define RSTMGR_NANDECC_RSTLINE 301
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#define RSTMGR_SDMMCECC_RSTLINE 303
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#define RSTMGR_DMA_RSTLINE 304
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#define RSTMGR_SPIM0_RSTLINE 305
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#define RSTMGR_SPIM1_RSTLINE 306
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#define RSTMGR_SPIS0_RSTLINE 307
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#define RSTMGR_SPIS1_RSTLINE 308
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#define RSTMGR_DMAECC_RSTLINE 309
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#define RSTMGR_EMACPTP_RSTLINE 310
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#define RSTMGR_DMAIF0_RSTLINE 312
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#define RSTMGR_DMAIF1_RSTLINE 313
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#define RSTMGR_DMAIF2_RSTLINE 314
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#define RSTMGR_DMAIF3_RSTLINE 315
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#define RSTMGR_DMAIF4_RSTLINE 316
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#define RSTMGR_DMAIF5_RSTLINE 317
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#define RSTMGR_DMAIF6_RSTLINE 318
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#define RSTMGR_DMAIF7_RSTLINE 319
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#define RSTMGR_WATCHDOG0_RSTLINE 320
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#define RSTMGR_WATCHDOG1_RSTLINE 321
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#define RSTMGR_WATCHDOG2_RSTLINE 322
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#define RSTMGR_WATCHDOG3_RSTLINE 323
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#define RSTMGR_L4SYSTIMER0_RSTLINE 324
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#define RSTMGR_L4SYSTIMER1_RSTLINE 325
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#define RSTMGR_SPTIMER0_RSTLINE 326
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#define RSTMGR_SPTIMER1_RSTLINE 327
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#define RSTMGR_I2C0_RSTLINE 328
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#define RSTMGR_I2C1_RSTLINE 329
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#define RSTMGR_I2C2_RSTLINE 330
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#define RSTMGR_I2C3_RSTLINE 331
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#define RSTMGR_I2C4_RSTLINE 332
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#define RSTMGR_I3C0_RSTLINE 333
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#define RSTMGR_I3C1_RSTLINE 334
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#define RSTMGR_UART0_RSTLINE 336
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#define RSTMGR_UART1_RSTLINE 337
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#define RSTMGR_GPIO0_RSTLINE 344
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#define RSTMGR_GPIO1_RSTLINE 345
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#define RSTMGR_WATCHDOG4_RSTLINE 346
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#define RSTMGR_SOC2FPGA_RSTLINE 352
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#define RSTMGR_LWSOC2FPGA_RSTLINE 353
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#define RSTMGR_FPGA2SOC_RSTLINE 354
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#define RSTMGR_FPGA2SDRAM_RSTLINE 355
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#define RSTMGR_MPFE_RSTLINE 358
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#define RSTMGR_DBG_RST_RSTLINE 480
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#define RSTMGR_SOC2FPGA_WARM_RSTLINE 608
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#define RSTMGR_LWSOC2FPGA_WARM_RSTLINE 609
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#define RSTMGR_FPGA2SOC_WARM_RSTLINE 610
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#define RSTMGR_FPGA2SDRAM_WARM_RSTLINE 611
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#define RSTMGR_MPFE_WARM_RSTLINE 614
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_ */
zephyr
dt-bindings
reset
intel_socfpga_reset.h
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