Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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imx_spc.h
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1/*
2 * Copyright (c) 2021, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8/*
9 * Setpoint definitions for IMX Set point controller. The SPC uses a series
10 * of set points to determine the clock speeds and states of cores, as well
11 * as which peripherals to gate clocks to. Higher values correspond to more
12 * power saving. See your SOC's datasheet for specifics of what peripherals
13 * have their clocks gated at each set point.
14 *
15 * Set point control is implemented at the soc level (see pm_state_set())
16 */
17
18#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
19#define ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
20
21#define IMX_GPC_RUN 0x0
22#define IMX_GPC_WAIT 0x1
23#define IMX_GPC_STOP 0x2
24#define IMX_GPC_SUSPEND 0x3
25
26
27#define IMX_SPC_MASK 0xF0
28#define IMX_SPC_SHIFT 4
29#define IMX_GPC_MODE_MASK 0xF
30
31#define IMX_SPC(x) ((x & IMX_SPC_MASK) >> IMX_SPC_SHIFT)
32#define IMX_GPC_MODE(x) (x & IMX_GPC_MODE_MASK)
33
34#define IMX_SPC_0 0x00
35#define IMX_SPC_1 0x10
36#define IMX_SPC_2 0x20
37#define IMX_SPC_3 0x30
38#define IMX_SPC_4 0x40
39#define IMX_SPC_5 0x50
40#define IMX_SPC_6 0x60
41#define IMX_SPC_7 0x70
42#define IMX_SPC_8 0x80
43#define IMX_SPC_9 0x90
44#define IMX_SPC_10 0xA0
45#define IMX_SPC_11 0xB0
46#define IMX_SPC_12 0xC0
47#define IMX_SPC_13 0xD0
48#define IMX_SPC_14 0xE0
49#define IMX_SPC_15 0xF0
50
51
52#define IMX_SPC_SET_POINT_0_RUN (IMX_SPC_0 | IMX_GPC_RUN)
53#define IMX_SPC_SET_POINT_0_WAIT (IMX_SPC_0 | IMX_GPC_WAIT)
54#define IMX_SPC_SET_POINT_0_STOP (IMX_SPC_0 | IMX_GPC_STOP)
55#define IMX_SPC_SET_POINT_0_SUSPEND (IMX_SPC_0 | IMX_GPC_SUSPEND)
56#define IMX_SPC_SET_POINT_1_RUN (IMX_SPC_1 | IMX_GPC_RUN)
57#define IMX_SPC_SET_POINT_1_WAIT (IMX_SPC_1 | IMX_GPC_WAIT)
58#define IMX_SPC_SET_POINT_1_STOP (IMX_SPC_1 | IMX_GPC_STOP)
59#define IMX_SPC_SET_POINT_1_SUSPEND (IMX_SPC_1 | IMX_GPC_SUSPEND)
60#define IMX_SPC_SET_POINT_2_RUN (IMX_SPC_2 | IMX_GPC_RUN)
61#define IMX_SPC_SET_POINT_2_WAIT (IMX_SPC_2 | IMX_GPC_WAIT)
62#define IMX_SPC_SET_POINT_2_STOP (IMX_SPC_2 | IMX_GPC_STOP)
63#define IMX_SPC_SET_POINT_2_SUSPEND (IMX_SPC_2 | IMX_GPC_SUSPEND)
64#define IMX_SPC_SET_POINT_3_RUN (IMX_SPC_3 | IMX_GPC_RUN)
65#define IMX_SPC_SET_POINT_3_WAIT (IMX_SPC_3 | IMX_GPC_WAIT)
66#define IMX_SPC_SET_POINT_3_STOP (IMX_SPC_3 | IMX_GPC_STOP)
67#define IMX_SPC_SET_POINT_3_SUSPEND (IMX_SPC_3 | IMX_GPC_SUSPEND)
68#define IMX_SPC_SET_POINT_4_RUN (IMX_SPC_4 | IMX_GPC_RUN)
69#define IMX_SPC_SET_POINT_4_WAIT (IMX_SPC_4 | IMX_GPC_WAIT)
70#define IMX_SPC_SET_POINT_4_STOP (IMX_SPC_4 | IMX_GPC_STOP)
71#define IMX_SPC_SET_POINT_4_SUSPEND (IMX_SPC_4 | IMX_GPC_SUSPEND)
72#define IMX_SPC_SET_POINT_5_RUN (IMX_SPC_5 | IMX_GPC_RUN)
73#define IMX_SPC_SET_POINT_5_WAIT (IMX_SPC_5 | IMX_GPC_WAIT)
74#define IMX_SPC_SET_POINT_5_STOP (IMX_SPC_5 | IMX_GPC_STOP)
75#define IMX_SPC_SET_POINT_5_SUSPEND (IMX_SPC_5 | IMX_GPC_SUSPEND)
76#define IMX_SPC_SET_POINT_6_RUN (IMX_SPC_6 | IMX_GPC_RUN)
77#define IMX_SPC_SET_POINT_6_WAIT (IMX_SPC_6 | IMX_GPC_WAIT)
78#define IMX_SPC_SET_POINT_6_STOP (IMX_SPC_6 | IMX_GPC_STOP)
79#define IMX_SPC_SET_POINT_6_SUSPEND (IMX_SPC_6 | IMX_GPC_SUSPEND)
80#define IMX_SPC_SET_POINT_7_RUN (IMX_SPC_7 | IMX_GPC_RUN)
81#define IMX_SPC_SET_POINT_7_WAIT (IMX_SPC_7 | IMX_GPC_WAIT)
82#define IMX_SPC_SET_POINT_7_STOP (IMX_SPC_7 | IMX_GPC_STOP)
83#define IMX_SPC_SET_POINT_7_SUSPEND (IMX_SPC_7 | IMX_GPC_SUSPEND)
84#define IMX_SPC_SET_POINT_8_RUN (IMX_SPC_8 | IMX_GPC_RUN)
85#define IMX_SPC_SET_POINT_8_WAIT (IMX_SPC_8 | IMX_GPC_WAIT)
86#define IMX_SPC_SET_POINT_8_STOP (IMX_SPC_8 | IMX_GPC_STOP)
87#define IMX_SPC_SET_POINT_8_SUSPEND (IMX_SPC_8 | IMX_GPC_SUSPEND)
88#define IMX_SPC_SET_POINT_9_RUN (IMX_SPC_9 | IMX_GPC_RUN)
89#define IMX_SPC_SET_POINT_9_WAIT (IMX_SPC_9 | IMX_GPC_WAIT)
90#define IMX_SPC_SET_POINT_9_STOP (IMX_SPC_9 | IMX_GPC_STOP)
91#define IMX_SPC_SET_POINT_9_SUSPEND (IMX_SPC_9 | IMX_GPC_SUSPEND)
92#define IMX_SPC_SET_POINT_10_RUN (IMX_SPC_10 | IMX_GPC_RUN)
93#define IMX_SPC_SET_POINT_10_WAIT (IMX_SPC_10 | IMX_GPC_WAIT)
94#define IMX_SPC_SET_POINT_10_STOP (IMX_SPC_10 | IMX_GPC_STOP)
95#define IMX_SPC_SET_POINT_10_SUSPEND (IMX_SPC_10 | IMX_GPC_SUSPEND)
96#define IMX_SPC_SET_POINT_11_RUN (IMX_SPC_11 | IMX_GPC_RUN)
97#define IMX_SPC_SET_POINT_11_WAIT (IMX_SPC_11 | IMX_GPC_WAIT)
98#define IMX_SPC_SET_POINT_11_STOP (IMX_SPC_11 | IMX_GPC_STOP)
99#define IMX_SPC_SET_POINT_11_SUSPEND (IMX_SPC_11 | IMX_GPC_SUSPEND)
100#define IMX_SPC_SET_POINT_12_RUN (IMX_SPC_12 | IMX_GPC_RUN)
101#define IMX_SPC_SET_POINT_12_WAIT (IMX_SPC_12 | IMX_GPC_WAIT)
102#define IMX_SPC_SET_POINT_12_STOP (IMX_SPC_12 | IMX_GPC_STOP)
103#define IMX_SPC_SET_POINT_12_SUSPEND (IMX_SPC_12 | IMX_GPC_SUSPEND)
104#define IMX_SPC_SET_POINT_13_RUN (IMX_SPC_13 | IMX_GPC_RUN)
105#define IMX_SPC_SET_POINT_13_WAIT (IMX_SPC_13 | IMX_GPC_WAIT)
106#define IMX_SPC_SET_POINT_13_STOP (IMX_SPC_13 | IMX_GPC_STOP)
107#define IMX_SPC_SET_POINT_13_SUSPEND (IMX_SPC_13 | IMX_GPC_SUSPEND)
108#define IMX_SPC_SET_POINT_14_RUN (IMX_SPC_14 | IMX_GPC_RUN)
109#define IMX_SPC_SET_POINT_14_WAIT (IMX_SPC_14 | IMX_GPC_WAIT)
110#define IMX_SPC_SET_POINT_14_STOP (IMX_SPC_14 | IMX_GPC_STOP)
111#define IMX_SPC_SET_POINT_14_SUSPEND (IMX_SPC_14 | IMX_GPC_SUSPEND)
112#define IMX_SPC_SET_POINT_15_RUN (IMX_SPC_15 | IMX_GPC_RUN)
113#define IMX_SPC_SET_POINT_15_WAIT (IMX_SPC_15 | IMX_GPC_WAIT)
114#define IMX_SPC_SET_POINT_15_STOP (IMX_SPC_15 | IMX_GPC_STOP)
115#define IMX_SPC_SET_POINT_15_SUSPEND (IMX_SPC_15 | IMX_GPC_SUSPEND)
116
117
118#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ */