Zephyr API Documentation
4.2.99
A Scalable Open Source RTOS
4.2.99
Toggle main menu visibility
Main Page
Related Pages
Topics
Data Structures
Data Structures
Data Structure Index
Data Fields
All
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Functions
Variables
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Enumerations
Enumerator
Files
File List
Globals
All
$
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Functions
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Variables
$
a
b
c
d
f
g
h
i
k
l
m
n
o
p
r
s
t
u
x
z
Typedefs
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Enumerations
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
r
s
t
u
v
w
x
z
Enumerator
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
r
s
t
u
v
w
x
z
Macros
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
•
All
Data Structures
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Macros
Modules
Pages
Loading...
Searching...
No Matches
imx8qm-pinctrl.h
Go to the documentation of this file.
1
/*
2
* Copyright 2023, 2025 NXP
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
7
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
8
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
9
10
/* values for pad field */
11
#define SC_P_UART0_RTS_B 23
12
#define SC_P_UART0_CTS_B 24
13
#define SC_P_ESAI0_FSR 104
14
#define SC_P_ESAI0_FST 105
15
#define SC_P_ESAI0_SCKR 106
16
#define SC_P_ESAI0_SCKT 107
17
#define SC_P_ESAI0_TX0 108
18
#define SC_P_ESAI0_TX1 109
19
#define SC_P_ESAI0_TX2_RX3 110
20
#define SC_P_ESAI0_TX3_RX2 111
21
#define SC_P_ESAI0_TX4_RX1 112
22
#define SC_P_ESAI0_TX5_RX0 113
23
#define SC_P_SAI1_RXD 128
24
#define SC_P_SAI1_TXC 130
25
#define SC_P_SAI1_TXD 131
26
#define SC_P_SAI1_TXFS 132
27
28
/* mux values */
29
#define IMX8QM_DMA_LPUART2_RX_UART0_RTS_B 2
/* UART0_RTS_B ---> DMA_LPUART2_RX */
30
#define IMX8QM_DMA_LPUART2_TX_UART0_CTS_B 2
/* DMA_LPUART2_TX ---> UART0_CTS_B */
31
#define IMX8QM_AUD_SAI1_RXD_SAI1_RXD 0
/* AUD_SAI1_RXD <--- SAI1_RXD */
32
#define IMX8QM_AUD_SAI1_TXC_SAI1_TXC 0
/* AUD_SAI1_TXC <---> SAI1_TXC */
33
#define IMX8QM_AUD_SAI1_TXD_SAI1_TXD 0
/* AUD_SAI1_TXD ---> SAI1_TXD */
34
#define IMX8QM_AUD_SAI1_TXFS_SAI1_TXFS 0
/* AUD_SAI1_TXFS <---> SAI1_TXFS */
35
#define IMX8QM_AUD_ESAI0_FSR_ESAI0_FSR 0
36
#define IMX8QM_AUD_ESAI0_FST_ESAI0_FST 0
37
#define IMX8QM_AUD_ESAI0_SCKR_ESAI0_SCKR 0
38
#define IMX8QM_AUD_ESAI0_SCKT_ESAI0_SCKT 0
39
#define IMX8QM_AUD_ESAI0_TX0_ESAI_TX0 0
40
#define IMX8QM_AUD_ESAI0_TX1_ESAI_TX1 0
41
#define IMX8QM_AUD_ESAI0_TX2_RX3_ESAI0_TX2_RX3 0
42
#define IMX8QM_AUD_ESAI0_TX3_RX2_ESAI0_TX3_RX2 0
43
#define IMX8QM_AUD_ESAI0_TX4_RX1_ESAI0_TX4_RX1 0
44
#define IMX8QM_AUD_ESAI0_TX5_RX0_ESAI0_TX5_RX0 0
45
46
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_ */
zephyr
dt-bindings
pinctrl
imx8qm-pinctrl.h
Generated on
for Zephyr API Documentation by
1.14.0