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A Scalable Open Source RTOS
4.1.99
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ifx_cat1-pinctrl.h
Go to the documentation of this file.
1
/* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
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#define SOC_PINMUX_PORT_POS (0)
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#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
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#define SOC_PINMUX_PIN_POS (8)
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#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
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#define SOC_PINMUX_HSIOM_FUNC_POS (16)
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#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
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#define SOC_PINMUX_SIGNAL_POS (24)
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#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
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#define HSIOM_SEL_GPIO (0)
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#define HSIOM_SEL_GPIO_DSI (1)
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#define HSIOM_SEL_DSI_DSI (2)
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#define HSIOM_SEL_DSI_GPIO (3)
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#define HSIOM_SEL_AMUXA (4)
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#define HSIOM_SEL_AMUXB (5)
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#define HSIOM_SEL_AMUXA_DSI (6)
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#define HSIOM_SEL_AMUXB_DSI (7)
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#define HSIOM_SEL_ACT_0 (8)
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#define HSIOM_SEL_ACT_1 (9)
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#define HSIOM_SEL_ACT_2 (10)
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#define HSIOM_SEL_ACT_3 (11)
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#define HSIOM_SEL_DS_0 (12)
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#define HSIOM_SEL_DS_1 (13)
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#define HSIOM_SEL_DS_2 (14)
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#define HSIOM_SEL_DS_3 (15)
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#define HSIOM_SEL_ACT_4 (16)
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#define HSIOM_SEL_ACT_5 (17)
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#define HSIOM_SEL_ACT_6 (18)
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#define HSIOM_SEL_ACT_7 (19)
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#define HSIOM_SEL_ACT_8 (20)
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#define HSIOM_SEL_ACT_9 (21)
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#define HSIOM_SEL_ACT_10 (22)
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#define HSIOM_SEL_ACT_11 (23)
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#define HSIOM_SEL_ACT_12 (24)
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#define HSIOM_SEL_ACT_13 (25)
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#define HSIOM_SEL_ACT_14 (26)
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#define HSIOM_SEL_ACT_15 (27)
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#define HSIOM_SEL_DS_4 (28)
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#define HSIOM_SEL_DS_5 (29)
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#define HSIOM_SEL_DS_6 (30)
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#define HSIOM_SEL_DS_7 (31)
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#define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal) \
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CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal
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#define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal) \
…
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#define DT_CAT1_PINMUX(port, pin, hsiom) \
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((port << SOC_PINMUX_PORT_POS) | \
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(pin << SOC_PINMUX_PIN_POS) | \
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(hsiom << SOC_PINMUX_HSIOM_FUNC_POS))
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#define DT_CAT1_PINMUX(port, pin, hsiom) \
…
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/* Redefine DT GPIO label (Px) to CYHAL port macros (CYHAL_PORT_x) */
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#define P0 CYHAL_PORT_0
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#define P1 CYHAL_PORT_1
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#define P2 CYHAL_PORT_2
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#define P3 CYHAL_PORT_3
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#define P4 CYHAL_PORT_4
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#define P5 CYHAL_PORT_5
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#define P6 CYHAL_PORT_6
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#define P7 CYHAL_PORT_7
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#define P8 CYHAL_PORT_8
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#define P9 CYHAL_PORT_9
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#define P10 CYHAL_PORT_10
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#define P11 CYHAL_PORT_11
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#define P12 CYHAL_PORT_12
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#define P13 CYHAL_PORT_13
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#define P14 CYHAL_PORT_14
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#define P15 CYHAL_PORT_15
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#define P16 CYHAL_PORT_16
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#define P17 CYHAL_PORT_17
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#define P18 CYHAL_PORT_18
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#define P19 CYHAL_PORT_19
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#define P20 CYHAL_PORT_20
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/* Returns CYHAL GPIO from Board device tree GPIO configuration
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* CYHAL_GET_GPIO(port_number, pin_number),
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* port_number = ((REG ADDR of node) - (REG ADDR of gpio_prt0)) / (REG SIZE of gpio_prt0)
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* pin_number = DT_PHA_BY_IDX(node, gpios_prop, 0, pin)
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*/
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#define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop) \
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CYHAL_GET_GPIO( \
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(DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \
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DT_PHA_BY_IDX(node, gpios_prop, 0, pin) \
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)
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#define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop) \
…
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_ */
zephyr
dt-bindings
pinctrl
ifx_cat1-pinctrl.h
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