PCIe Controller

Interfaces for PCIe Controllers. More...

Topics
	PCIe Controller Driver Backend API

Data Structures
struct	pcie_ctrl_config
	Structure describing a device that supports the PCI Express Controller API. More...

Macros
#define	PCIE_RANGE_FORMAT(node_id, idx)

Functions
static uint32_t	pcie_ctrl_conf_read (const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
	Read a 32-bit word from an endpoint's configuration space.
static void	pcie_ctrl_conf_write (const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
	Write a 32-bit word to an endpoint's configuration space.
static bool	pcie_ctrl_region_allocate (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t *bar_bus_addr)
	Allocate a memory region subset for an endpoint Base Address Register.
static bool	pcie_ctrl_region_get_allocate_base (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t *bar_base_addr)
	Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.
static bool	pcie_ctrl_region_translate (const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t *bar_addr)
	Translate an endpoint Base Address Register bus-centric address into Physical address.
static uint8_t	pcie_ctrl_msi_device_setup (const struct device *dev, unsigned int priority, msi_vector_t *vectors, uint8_t n_vector)
	Configure the given PCI endpoint to generate MSIs.

Detailed Description

Interfaces for PCIe Controllers.

Macro Definition Documentation

PCIE_RANGE_FORMAT

#define PCIE_RANGE_FORMAT	(		node_id,
			idx )

#include <zephyr/drivers/pcie/controller.h>

Value:

{                                                                                       \
        .flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx),                        \
        .pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx),              \
        .host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx),             \
        .map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx),                            \
},

Function Documentation

pcie_ctrl_conf_read()

uint32_t pcie_ctrl_conf_read ( const struct device * dev, pcie_bdf_t bdf, unsigned int reg )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Read a 32-bit word from an endpoint's configuration space.

Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)

Returns

the word read (0xFFFFFFFFU if nonexistent endpoint or word)

pcie_ctrl_conf_write()

void pcie_ctrl_conf_write ( const struct device * dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Write a 32-bit word to an endpoint's configuration space.

Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller configuration space access method (I/O port, memory mapped or custom method)

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
reg	the configuration word index (not address)
data	the value to write

pcie_ctrl_msi_device_setup()

uint8_t pcie_ctrl_msi_device_setup ( const struct device * dev, unsigned int priority, msi_vector_t * vectors, uint8_t n_vector )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Configure the given PCI endpoint to generate MSIs.

Attention

Available only when the following Kconfig option is enabled: CONFIG_PCIE_MSI.

Parameters

dev	PCI Express Controller device pointer
priority	MSI priority
vectors	an array of allocated vector(s)
n_vector	the size of the vector array

Returns

the number of vectors allocated

pcie_ctrl_region_allocate()

bool pcie_ctrl_region_allocate ( const struct device * dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t * bar_bus_addr )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Allocate a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

This call allocates such zone in the PCI Express Controller memory regions if such region is available and space is still available.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_size	Size in bytes of the Base Address Register as returned by HW
bar_bus_addr	bus-centric address allocated to be written in the BAR register

Returns

True if allocation was possible, False if allocation failed

pcie_ctrl_region_get_allocate_base()

bool pcie_ctrl_region_get_allocate_base ( const struct device * dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t * bar_base_addr )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Function called to get the current allocation base of a memory region subset for an endpoint Base Address Register.

When enumerating PCIe Endpoints, Type1 bridge endpoints requires a range of memory allocated by all endpoints in the bridged bus.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
align	size to take in account for alignment
bar_base_addr	bus-centric address allocation base

Returns

True if allocation was possible, False if allocation failed

pcie_ctrl_region_translate()

bool pcie_ctrl_region_translate ( const struct device * dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t * bar_addr )

inlinestatic

#include <zephyr/drivers/pcie/controller.h>

Translate an endpoint Base Address Register bus-centric address into Physical address.

When enumerating PCIe Endpoints, Type0 endpoints can require up to 6 memory zones via the Base Address Registers from I/O or Memory types.

The bus-centric address set in this BAR register is not necessarily accessible from the CPU, thus must be translated by using the PCI Express Controller memory regions translation ranges to permit mapping from the CPU.

Parameters

dev	PCI Express Controller device pointer
bdf	PCI(e) endpoint
mem	True if the BAR is of memory type
mem64	True if the BAR is of 64bit memory type
bar_bus_addr	bus-centric address written in the BAR register
bar_addr	CPU-centric address translated from the bus-centric address

Returns

True if translation was possible, False if translation failed