Ethernet MII Support Functions

Ethernet MII (media independent interface) functions. More...

Files
file	mii.h
	Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers.

Macros
#define	MII_ADVERTISE_ALL
	Advertise all speeds.

MII management registers
#define	MII_BMCR   0x0
	Basic Mode Control Register.
#define	MII_BMSR   0x1
	Basic Mode Status Register.
#define	MII_PHYID1R   0x2
	PHY ID 1 Register.
#define	MII_PHYID2R   0x3
	PHY ID 2 Register.
#define	MII_ANAR   0x4
	Auto-Negotiation Advertisement Register.
#define	MII_ANLPAR   0x5
	Auto-Negotiation Link Partner Ability Reg.
#define	MII_ANER   0x6
	Auto-Negotiation Expansion Register.
#define	MII_ANNPTR   0x7
	Auto-Negotiation Next Page Transmit Register.
#define	MII_ANLPRNPR   0x8
	Auto-Negotiation Link Partner Received Next Page Reg.
#define	MII_1KTCR   0x9
	1000BASE-T Control Register
#define	MII_1KSTSR   0xa
	1000BASE-T Status Register
#define	MII_MMD_ACR   0xd
	MMD Access Control Register.
#define	MII_MMD_AADR   0xe
	MMD Access Address Data Register.
#define	MII_ESTAT   0xf
	Extended Status Register.

Basic Mode Control Register (BMCR) bit definitions
#define	MII_BMCR_RESET_BIT   15
	PHY reset bit position.
#define	MII_BMCR_LOOPBACK_BIT   14
	Loopback mode bit position.
#define	MII_BMCR_SPEED_LSB_BIT   13
	Speed selection LSB bit position.
#define	MII_BMCR_AUTONEG_ENABLE_BIT   12
	Auto-Negotiation enable bit position.
#define	MII_BMCR_POWER_DOWN_BIT   11
	Power-down bit position.
#define	MII_BMCR_ISOLATE_BIT   10
	Isolate bit position.
#define	MII_BMCR_AUTONEG_RESTART_BIT   9
	Restart Auto-Negotiation bit position.
#define	MII_BMCR_DUPLEX_MODE_BIT   8
	Duplex mode bit position.
#define	MII_BMCR_SPEED_MSB_BIT   6
	Speed selection MSB bit position.
#define	MII_BMCR_RESET   BIT(MII_BMCR_RESET_BIT)
	PHY reset.
#define	MII_BMCR_LOOPBACK   BIT(MII_BMCR_LOOPBACK_BIT)
	Enable loopback mode.
#define	MII_BMCR_SPEED_LSB   BIT(MII_BMCR_SPEED_LSB_BIT)
	10=1000Mbps 01=100Mbps; 00=10Mbps
#define	MII_BMCR_AUTONEG_ENABLE   BIT(MII_BMCR_AUTONEG_ENABLE_BIT)
	Auto-Negotiation enable.
#define	MII_BMCR_POWER_DOWN   BIT(MII_BMCR_POWER_DOWN_BIT)
	Power down mode.
#define	MII_BMCR_ISOLATE   BIT(MII_BMCR_ISOLATE_BIT)
	Isolate electrically PHY from MII.
#define	MII_BMCR_AUTONEG_RESTART   BIT(MII_BMCR_AUTONEG_RESTART_BIT)
	Restart auto-negotiation.
#define	MII_BMCR_DUPLEX_MODE   BIT(MII_BMCR_DUPLEX_MODE_BIT)
	Full duplex mode.
#define	MII_BMCR_SPEED_MSB   BIT(MII_BMCR_SPEED_MSB_BIT)
	10=1000Mbps 01=100Mbps; 00=10Mbps
#define	MII_BMCR_SPEED_MASK   (MII_BMCR_SPEED_MSB | MII_BMCR_SPEED_LSB)
	Link Speed Field.
#define	MII_BMCR_SPEED_10   0
	Select speed 10 Mb/s.
#define	MII_BMCR_SPEED_100   BIT(MII_BMCR_SPEED_LSB_BIT)
	Select speed 100 Mb/s.
#define	MII_BMCR_SPEED_1000   BIT(MII_BMCR_SPEED_MSB_BIT)
	Select speed 1000 Mb/s.

Basic Mode Status Register (BMSR) bit definitions
#define	MII_BMSR_100BASE_T4_BIT   15
	100BASE-T4 capable bit position
#define	MII_BMSR_100BASE_X_FULL_BIT   14
	100BASE-X full duplex capable bit position
#define	MII_BMSR_100BASE_X_HALF_BIT   13
	100BASE-X half duplex capable bit position
#define	MII_BMSR_10_FULL_BIT   12
	10 Mb/s full duplex capable bit position
#define	MII_BMSR_10_HALF_BIT   11
	10 Mb/s half duplex capable bit position
#define	MII_BMSR_100BASE_T2_FULL_BIT   10
	100BASE-T2 full duplex capable bit position
#define	MII_BMSR_100BASE_T2_HALF_BIT   9
	100BASE-T2 half duplex capable bit position
#define	MII_BMSR_EXTEND_STATUS_BIT   8
	Extended status information bit position.
#define	MII_BMSR_MF_PREAMB_SUPPR_BIT   6
	Preamble suppression capable bit position.
#define	MII_BMSR_AUTONEG_COMPLETE_BIT   5
	Auto-Negotiation complete bit position.
#define	MII_BMSR_REMOTE_FAULT_BIT   4
	Remote fault bit position.
#define	MII_BMSR_AUTONEG_ABILITY_BIT   3
	Auto-Negotiation ability bit position.
#define	MII_BMSR_LINK_STATUS_BIT   2
	Link status bit position.
#define	MII_BMSR_JABBER_DETECT_BIT   1
	Jabber detect bit position.
#define	MII_BMSR_EXTEND_CAPAB_BIT   0
	Extended capability bit position.
#define	MII_BMSR_100BASE_T4   BIT(MII_BMSR_100BASE_T4_BIT)
	100BASE-T4 capable
#define	MII_BMSR_100BASE_X_FULL   BIT(MII_BMSR_100BASE_X_FULL_BIT)
	100BASE-X full duplex capable
#define	MII_BMSR_100BASE_X_HALF   BIT(MII_BMSR_100BASE_X_HALF_BIT)
	100BASE-X half duplex capable
#define	MII_BMSR_10_FULL   BIT(MII_BMSR_10_FULL_BIT)
	10 Mb/s full duplex capable
#define	MII_BMSR_10_HALF   BIT(MII_BMSR_10_HALF_BIT)
	10 Mb/s half duplex capable
#define	MII_BMSR_100BASE_T2_FULL   BIT(MII_BMSR_100BASE_T2_FULL_BIT)
	100BASE-T2 full duplex capable
#define	MII_BMSR_100BASE_T2_HALF   BIT(MII_BMSR_100BASE_T2_HALF_BIT)
	100BASE-T2 half duplex capable
#define	MII_BMSR_EXTEND_STATUS   BIT(MII_BMSR_EXTEND_STATUS_BIT)
	Extend status information in reg 15.
#define	MII_BMSR_MF_PREAMB_SUPPR   BIT(MII_BMSR_MF_PREAMB_SUPPR_BIT)
	PHY accepts management frames with preamble suppressed.
#define	MII_BMSR_AUTONEG_COMPLETE   BIT(MII_BMSR_AUTONEG_COMPLETE_BIT)
	Auto-negotiation process completed.
#define	MII_BMSR_REMOTE_FAULT   BIT(MII_BMSR_REMOTE_FAULT_BIT)
	Remote fault detected.
#define	MII_BMSR_AUTONEG_ABILITY   BIT(MII_BMSR_AUTONEG_ABILITY_BIT)
	PHY is able to perform Auto-Negotiation.
#define	MII_BMSR_LINK_STATUS   BIT(MII_BMSR_LINK_STATUS_BIT)
	Link is up.
#define	MII_BMSR_JABBER_DETECT   BIT(MII_BMSR_JABBER_DETECT_BIT)
	Jabber condition detected.
#define	MII_BMSR_EXTEND_CAPAB   BIT(MII_BMSR_EXTEND_CAPAB_BIT)
	Extended register capabilities.

Auto-negotiation Advertisement (ANAR) and Link Partner Ability
(ANLPAR) Register bit definitions
#define	MII_ADVERTISE_NEXT_PAGE_BIT   15
	Next page bit position.
#define	MII_ADVERTISE_LPACK_BIT   14
	Link partner acknowledge bit position.
#define	MII_ADVERTISE_REMOTE_FAULT_BIT   13
	Remote fault bit position.
#define	MII_ADVERTISE_ASYM_PAUSE_BIT   11
	Asymmetric pause bit position.
#define	MII_ADVERTISE_PAUSE_BIT   10
	Pause bit position.
#define	MII_ADVERTISE_100BASE_T4_BIT   9
	100BASE-T4 support bit position
#define	MII_ADVERTISE_100_FULL_BIT   8
	100BASE-X full duplex support bit position
#define	MII_ADVERTISE_100_HALF_BIT   7
	100BASE-X half duplex support bit position
#define	MII_ADVERTISE_10_FULL_BIT   6
	10 Mb/s full duplex support bit position
#define	MII_ADVERTISE_10_HALF_BIT   5
	10 Mb/s half duplex support bit position
#define	MII_ADVERTISE_NEXT_PAGE   BIT(MII_ADVERTISE_NEXT_PAGE_BIT)
	Next page.
#define	MII_ADVERTISE_LPACK   BIT(MII_ADVERTISE_LPACK_BIT)
	Link partner acknowledge response.
#define	MII_ADVERTISE_REMOTE_FAULT   BIT(MII_ADVERTISE_REMOTE_FAULT_BIT)
	Remote fault.
#define	MII_ADVERTISE_ASYM_PAUSE   BIT(MII_ADVERTISE_ASYM_PAUSE_BIT)
	Try for asymmetric pause.
#define	MII_ADVERTISE_PAUSE   BIT(MII_ADVERTISE_PAUSE_BIT)
	Try for pause.
#define	MII_ADVERTISE_100BASE_T4   BIT(MII_ADVERTISE_100BASE_T4_BIT)
	Try for 100BASE-T4 support.
#define	MII_ADVERTISE_100_FULL   BIT(MII_ADVERTISE_100_FULL_BIT)
	Try for 100BASE-X full duplex support.
#define	MII_ADVERTISE_100_HALF   BIT(MII_ADVERTISE_100_HALF_BIT)
	Try for 100BASE-X support.
#define	MII_ADVERTISE_10_FULL   BIT(MII_ADVERTISE_10_FULL_BIT)
	Try for 10 Mb/s full duplex support.
#define	MII_ADVERTISE_10_HALF   BIT(MII_ADVERTISE_10_HALF_BIT)
	Try for 10 Mb/s half duplex support.
#define	MII_ADVERTISE_SEL_MASK   (0x1F << 0)
	Selector Field Mask.
#define	MII_ADVERTISE_SEL_IEEE_802_3   0x01
	Selector Field.

1000BASE-T Control Register bit definitions
#define	MII_ADVERTISE_1000_FULL_BIT   9
	1000BASE-T full duplex support bit position
#define	MII_ADVERTISE_1000_HALF_BIT   8
	1000BASE-T half duplex support bit position
#define	MII_ADVERTISE_1000_FULL   BIT(MII_ADVERTISE_1000_FULL_BIT)
	Try for 1000BASE-T full duplex support.
#define	MII_ADVERTISE_1000_HALF   BIT(MII_ADVERTISE_1000_HALF_BIT)
	Try for 1000BASE-T half duplex support.

Extended Status Register bit definitions
#define	MII_ESTAT_1000BASE_X_FULL   BIT(15)
	1000BASE-X full-duplex capable
#define	MII_ESTAT_1000BASE_X_HALF   BIT(14)
	1000BASE-X half-duplex capable
#define	MII_ESTAT_1000BASE_T_FULL   BIT(13)
	1000BASE-T full-duplex capable
#define	MII_ESTAT_1000BASE_T_HALF   BIT(12)
	1000BASE-T half-duplex capable

MMD Access Control Register (MII_MMD_ACR) bit definitions
#define	MII_MMD_ACR_DEVAD_MASK   (0x1F << 0)
	DEVAD Mask.
#define	MII_MMD_ACR_ADDR   (0x00 << 14)
	Address.
#define	MII_MMD_ACR_DATA_NO_POS_INC   (0x01 << 14)
	Data, no post increment.
#define	MII_MMD_ACR_DATA_RW_POS_INC   (0x10 << 14)
	Data, post increment on reads and writes.
#define	MII_MMD_ACR_DATA_W_POS_INC   (0x11 << 14)
	Data, post increment on writes only.

Detailed Description

Ethernet MII (media independent interface) functions.

Since

1.7

Version

0.8.0

Macro Definition Documentation

MII_1KSTSR

#define MII_1KSTSR   0xa

#include <zephyr/net/mii.h>

1000BASE-T Status Register

MII_1KTCR

#define MII_1KTCR   0x9

#include <zephyr/net/mii.h>

1000BASE-T Control Register

MII_ADVERTISE_1000_FULL

#define MII_ADVERTISE_1000_FULL   BIT(MII_ADVERTISE_1000_FULL_BIT)

#include <zephyr/net/mii.h>

Try for 1000BASE-T full duplex support.

MII_ADVERTISE_1000_FULL_BIT

#define MII_ADVERTISE_1000_FULL_BIT   9

#include <zephyr/net/mii.h>

1000BASE-T full duplex support bit position

MII_ADVERTISE_1000_HALF

#define MII_ADVERTISE_1000_HALF   BIT(MII_ADVERTISE_1000_HALF_BIT)

#include <zephyr/net/mii.h>

Try for 1000BASE-T half duplex support.

MII_ADVERTISE_1000_HALF_BIT

#define MII_ADVERTISE_1000_HALF_BIT   8

#include <zephyr/net/mii.h>

1000BASE-T half duplex support bit position

MII_ADVERTISE_100_FULL

#define MII_ADVERTISE_100_FULL   BIT(MII_ADVERTISE_100_FULL_BIT)

#include <zephyr/net/mii.h>

Try for 100BASE-X full duplex support.

MII_ADVERTISE_100_FULL_BIT

#define MII_ADVERTISE_100_FULL_BIT   8

#include <zephyr/net/mii.h>

100BASE-X full duplex support bit position

MII_ADVERTISE_100_HALF

#define MII_ADVERTISE_100_HALF   BIT(MII_ADVERTISE_100_HALF_BIT)

#include <zephyr/net/mii.h>

Try for 100BASE-X support.

MII_ADVERTISE_100_HALF_BIT

#define MII_ADVERTISE_100_HALF_BIT   7

#include <zephyr/net/mii.h>

100BASE-X half duplex support bit position

MII_ADVERTISE_100BASE_T4

#define MII_ADVERTISE_100BASE_T4   BIT(MII_ADVERTISE_100BASE_T4_BIT)

#include <zephyr/net/mii.h>

Try for 100BASE-T4 support.

MII_ADVERTISE_100BASE_T4_BIT

#define MII_ADVERTISE_100BASE_T4_BIT   9

#include <zephyr/net/mii.h>

100BASE-T4 support bit position

MII_ADVERTISE_10_FULL

#define MII_ADVERTISE_10_FULL   BIT(MII_ADVERTISE_10_FULL_BIT)

#include <zephyr/net/mii.h>

Try for 10 Mb/s full duplex support.

MII_ADVERTISE_10_FULL_BIT

#define MII_ADVERTISE_10_FULL_BIT   6

#include <zephyr/net/mii.h>

10 Mb/s full duplex support bit position

MII_ADVERTISE_10_HALF

#define MII_ADVERTISE_10_HALF   BIT(MII_ADVERTISE_10_HALF_BIT)

#include <zephyr/net/mii.h>

Try for 10 Mb/s half duplex support.

MII_ADVERTISE_10_HALF_BIT

#define MII_ADVERTISE_10_HALF_BIT   5

#include <zephyr/net/mii.h>

10 Mb/s half duplex support bit position

MII_ADVERTISE_ALL

#define MII_ADVERTISE_ALL

#include <zephyr/net/mii.h>

Value:

(MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
MII_ADVERTISE_SEL_IEEE_802_3)

Advertise all speeds.

MII_ADVERTISE_ASYM_PAUSE

#define MII_ADVERTISE_ASYM_PAUSE   BIT(MII_ADVERTISE_ASYM_PAUSE_BIT)

#include <zephyr/net/mii.h>

Try for asymmetric pause.

MII_ADVERTISE_ASYM_PAUSE_BIT

#define MII_ADVERTISE_ASYM_PAUSE_BIT   11

#include <zephyr/net/mii.h>

Asymmetric pause bit position.

MII_ADVERTISE_LPACK

#define MII_ADVERTISE_LPACK   BIT(MII_ADVERTISE_LPACK_BIT)

#include <zephyr/net/mii.h>

Link partner acknowledge response.

MII_ADVERTISE_LPACK_BIT

#define MII_ADVERTISE_LPACK_BIT   14

#include <zephyr/net/mii.h>

Link partner acknowledge bit position.

MII_ADVERTISE_NEXT_PAGE

#define MII_ADVERTISE_NEXT_PAGE   BIT(MII_ADVERTISE_NEXT_PAGE_BIT)

#include <zephyr/net/mii.h>

Next page.

MII_ADVERTISE_NEXT_PAGE_BIT

#define MII_ADVERTISE_NEXT_PAGE_BIT   15

#include <zephyr/net/mii.h>

Next page bit position.

MII_ADVERTISE_PAUSE

#define MII_ADVERTISE_PAUSE   BIT(MII_ADVERTISE_PAUSE_BIT)

#include <zephyr/net/mii.h>

Try for pause.

MII_ADVERTISE_PAUSE_BIT

#define MII_ADVERTISE_PAUSE_BIT   10

#include <zephyr/net/mii.h>

Pause bit position.

MII_ADVERTISE_REMOTE_FAULT

#define MII_ADVERTISE_REMOTE_FAULT   BIT(MII_ADVERTISE_REMOTE_FAULT_BIT)

#include <zephyr/net/mii.h>

Remote fault.

MII_ADVERTISE_REMOTE_FAULT_BIT

#define MII_ADVERTISE_REMOTE_FAULT_BIT   13

#include <zephyr/net/mii.h>

Remote fault bit position.

MII_ADVERTISE_SEL_IEEE_802_3

#define MII_ADVERTISE_SEL_IEEE_802_3   0x01

#include <zephyr/net/mii.h>

Selector Field.

MII_ADVERTISE_SEL_MASK

#define MII_ADVERTISE_SEL_MASK   (0x1F << 0)

#include <zephyr/net/mii.h>

Selector Field Mask.

MII_ANAR

#define MII_ANAR   0x4

#include <zephyr/net/mii.h>

Auto-Negotiation Advertisement Register.

MII_ANER

#define MII_ANER   0x6

#include <zephyr/net/mii.h>

Auto-Negotiation Expansion Register.

MII_ANLPAR

#define MII_ANLPAR   0x5

#include <zephyr/net/mii.h>

Auto-Negotiation Link Partner Ability Reg.

MII_ANLPRNPR

#define MII_ANLPRNPR   0x8

#include <zephyr/net/mii.h>

Auto-Negotiation Link Partner Received Next Page Reg.

MII_ANNPTR

#define MII_ANNPTR   0x7

#include <zephyr/net/mii.h>

Auto-Negotiation Next Page Transmit Register.

MII_BMCR

#define MII_BMCR   0x0

#include <zephyr/net/mii.h>

Basic Mode Control Register.

MII_BMCR_AUTONEG_ENABLE

#define MII_BMCR_AUTONEG_ENABLE   BIT(MII_BMCR_AUTONEG_ENABLE_BIT)

#include <zephyr/net/mii.h>

Auto-Negotiation enable.

MII_BMCR_AUTONEG_ENABLE_BIT

#define MII_BMCR_AUTONEG_ENABLE_BIT   12

#include <zephyr/net/mii.h>

Auto-Negotiation enable bit position.

MII_BMCR_AUTONEG_RESTART

#define MII_BMCR_AUTONEG_RESTART   BIT(MII_BMCR_AUTONEG_RESTART_BIT)

#include <zephyr/net/mii.h>

Restart auto-negotiation.

MII_BMCR_AUTONEG_RESTART_BIT

#define MII_BMCR_AUTONEG_RESTART_BIT   9

#include <zephyr/net/mii.h>

Restart Auto-Negotiation bit position.

MII_BMCR_DUPLEX_MODE

#define MII_BMCR_DUPLEX_MODE   BIT(MII_BMCR_DUPLEX_MODE_BIT)

#include <zephyr/net/mii.h>

Full duplex mode.

MII_BMCR_DUPLEX_MODE_BIT

#define MII_BMCR_DUPLEX_MODE_BIT   8

#include <zephyr/net/mii.h>

Duplex mode bit position.

MII_BMCR_ISOLATE

#define MII_BMCR_ISOLATE   BIT(MII_BMCR_ISOLATE_BIT)

#include <zephyr/net/mii.h>

Isolate electrically PHY from MII.

MII_BMCR_ISOLATE_BIT

#define MII_BMCR_ISOLATE_BIT   10

#include <zephyr/net/mii.h>

Isolate bit position.

MII_BMCR_LOOPBACK

#define MII_BMCR_LOOPBACK   BIT(MII_BMCR_LOOPBACK_BIT)

#include <zephyr/net/mii.h>

Enable loopback mode.

MII_BMCR_LOOPBACK_BIT

#define MII_BMCR_LOOPBACK_BIT   14

#include <zephyr/net/mii.h>

Loopback mode bit position.

MII_BMCR_POWER_DOWN

#define MII_BMCR_POWER_DOWN   BIT(MII_BMCR_POWER_DOWN_BIT)

#include <zephyr/net/mii.h>

Power down mode.

MII_BMCR_POWER_DOWN_BIT

#define MII_BMCR_POWER_DOWN_BIT   11

#include <zephyr/net/mii.h>

Power-down bit position.

MII_BMCR_RESET

#define MII_BMCR_RESET   BIT(MII_BMCR_RESET_BIT)

#include <zephyr/net/mii.h>

PHY reset.

MII_BMCR_RESET_BIT

#define MII_BMCR_RESET_BIT   15

#include <zephyr/net/mii.h>

PHY reset bit position.

MII_BMCR_SPEED_10

#define MII_BMCR_SPEED_10   0

#include <zephyr/net/mii.h>

Select speed 10 Mb/s.

MII_BMCR_SPEED_100

#define MII_BMCR_SPEED_100   BIT(MII_BMCR_SPEED_LSB_BIT)

#include <zephyr/net/mii.h>

Select speed 100 Mb/s.

MII_BMCR_SPEED_1000

#define MII_BMCR_SPEED_1000   BIT(MII_BMCR_SPEED_MSB_BIT)

#include <zephyr/net/mii.h>

Select speed 1000 Mb/s.

MII_BMCR_SPEED_LSB

#define MII_BMCR_SPEED_LSB   BIT(MII_BMCR_SPEED_LSB_BIT)

#include <zephyr/net/mii.h>

10=1000Mbps 01=100Mbps; 00=10Mbps

MII_BMCR_SPEED_LSB_BIT

#define MII_BMCR_SPEED_LSB_BIT   13

#include <zephyr/net/mii.h>

Speed selection LSB bit position.

MII_BMCR_SPEED_MASK

#define MII_BMCR_SPEED_MASK   (MII_BMCR_SPEED_MSB | MII_BMCR_SPEED_LSB)

#include <zephyr/net/mii.h>

Link Speed Field.

MII_BMCR_SPEED_MSB

#define MII_BMCR_SPEED_MSB   BIT(MII_BMCR_SPEED_MSB_BIT)

#include <zephyr/net/mii.h>

10=1000Mbps 01=100Mbps; 00=10Mbps

MII_BMCR_SPEED_MSB_BIT

#define MII_BMCR_SPEED_MSB_BIT   6

#include <zephyr/net/mii.h>

Speed selection MSB bit position.

MII_BMSR

#define MII_BMSR   0x1

#include <zephyr/net/mii.h>

Basic Mode Status Register.

MII_BMSR_100BASE_T2_FULL

#define MII_BMSR_100BASE_T2_FULL   BIT(MII_BMSR_100BASE_T2_FULL_BIT)

#include <zephyr/net/mii.h>

100BASE-T2 full duplex capable

MII_BMSR_100BASE_T2_FULL_BIT

#define MII_BMSR_100BASE_T2_FULL_BIT   10

#include <zephyr/net/mii.h>

100BASE-T2 full duplex capable bit position

MII_BMSR_100BASE_T2_HALF

#define MII_BMSR_100BASE_T2_HALF   BIT(MII_BMSR_100BASE_T2_HALF_BIT)

#include <zephyr/net/mii.h>

100BASE-T2 half duplex capable

MII_BMSR_100BASE_T2_HALF_BIT

#define MII_BMSR_100BASE_T2_HALF_BIT   9

#include <zephyr/net/mii.h>

100BASE-T2 half duplex capable bit position

MII_BMSR_100BASE_T4

#define MII_BMSR_100BASE_T4   BIT(MII_BMSR_100BASE_T4_BIT)

#include <zephyr/net/mii.h>

100BASE-T4 capable

MII_BMSR_100BASE_T4_BIT

#define MII_BMSR_100BASE_T4_BIT   15

#include <zephyr/net/mii.h>

100BASE-T4 capable bit position

MII_BMSR_100BASE_X_FULL

#define MII_BMSR_100BASE_X_FULL   BIT(MII_BMSR_100BASE_X_FULL_BIT)

#include <zephyr/net/mii.h>

100BASE-X full duplex capable

MII_BMSR_100BASE_X_FULL_BIT

#define MII_BMSR_100BASE_X_FULL_BIT   14

#include <zephyr/net/mii.h>

100BASE-X full duplex capable bit position

MII_BMSR_100BASE_X_HALF

#define MII_BMSR_100BASE_X_HALF   BIT(MII_BMSR_100BASE_X_HALF_BIT)

#include <zephyr/net/mii.h>

100BASE-X half duplex capable

MII_BMSR_100BASE_X_HALF_BIT

#define MII_BMSR_100BASE_X_HALF_BIT   13

#include <zephyr/net/mii.h>

100BASE-X half duplex capable bit position

MII_BMSR_10_FULL

#define MII_BMSR_10_FULL   BIT(MII_BMSR_10_FULL_BIT)

#include <zephyr/net/mii.h>

10 Mb/s full duplex capable

MII_BMSR_10_FULL_BIT

#define MII_BMSR_10_FULL_BIT   12

#include <zephyr/net/mii.h>

10 Mb/s full duplex capable bit position

MII_BMSR_10_HALF

#define MII_BMSR_10_HALF   BIT(MII_BMSR_10_HALF_BIT)

#include <zephyr/net/mii.h>

10 Mb/s half duplex capable

MII_BMSR_10_HALF_BIT

#define MII_BMSR_10_HALF_BIT   11

#include <zephyr/net/mii.h>

10 Mb/s half duplex capable bit position

MII_BMSR_AUTONEG_ABILITY

#define MII_BMSR_AUTONEG_ABILITY   BIT(MII_BMSR_AUTONEG_ABILITY_BIT)

#include <zephyr/net/mii.h>

PHY is able to perform Auto-Negotiation.

MII_BMSR_AUTONEG_ABILITY_BIT

#define MII_BMSR_AUTONEG_ABILITY_BIT   3

#include <zephyr/net/mii.h>

Auto-Negotiation ability bit position.

MII_BMSR_AUTONEG_COMPLETE

#define MII_BMSR_AUTONEG_COMPLETE   BIT(MII_BMSR_AUTONEG_COMPLETE_BIT)

#include <zephyr/net/mii.h>

Auto-negotiation process completed.

MII_BMSR_AUTONEG_COMPLETE_BIT

#define MII_BMSR_AUTONEG_COMPLETE_BIT   5

#include <zephyr/net/mii.h>

Auto-Negotiation complete bit position.

MII_BMSR_EXTEND_CAPAB

#define MII_BMSR_EXTEND_CAPAB   BIT(MII_BMSR_EXTEND_CAPAB_BIT)

#include <zephyr/net/mii.h>

Extended register capabilities.

MII_BMSR_EXTEND_CAPAB_BIT

#define MII_BMSR_EXTEND_CAPAB_BIT   0

#include <zephyr/net/mii.h>

Extended capability bit position.

MII_BMSR_EXTEND_STATUS

#define MII_BMSR_EXTEND_STATUS   BIT(MII_BMSR_EXTEND_STATUS_BIT)

#include <zephyr/net/mii.h>

Extend status information in reg 15.

MII_BMSR_EXTEND_STATUS_BIT

#define MII_BMSR_EXTEND_STATUS_BIT   8

#include <zephyr/net/mii.h>

Extended status information bit position.

MII_BMSR_JABBER_DETECT

#define MII_BMSR_JABBER_DETECT   BIT(MII_BMSR_JABBER_DETECT_BIT)

#include <zephyr/net/mii.h>

Jabber condition detected.

MII_BMSR_JABBER_DETECT_BIT

#define MII_BMSR_JABBER_DETECT_BIT   1

#include <zephyr/net/mii.h>

Jabber detect bit position.

MII_BMSR_LINK_STATUS

#define MII_BMSR_LINK_STATUS   BIT(MII_BMSR_LINK_STATUS_BIT)

#include <zephyr/net/mii.h>

Link is up.

MII_BMSR_LINK_STATUS_BIT

#define MII_BMSR_LINK_STATUS_BIT   2

#include <zephyr/net/mii.h>

Link status bit position.

MII_BMSR_MF_PREAMB_SUPPR

#define MII_BMSR_MF_PREAMB_SUPPR   BIT(MII_BMSR_MF_PREAMB_SUPPR_BIT)

#include <zephyr/net/mii.h>

PHY accepts management frames with preamble suppressed.

MII_BMSR_MF_PREAMB_SUPPR_BIT

#define MII_BMSR_MF_PREAMB_SUPPR_BIT   6

#include <zephyr/net/mii.h>

Preamble suppression capable bit position.

MII_BMSR_REMOTE_FAULT

#define MII_BMSR_REMOTE_FAULT   BIT(MII_BMSR_REMOTE_FAULT_BIT)

#include <zephyr/net/mii.h>

Remote fault detected.

MII_BMSR_REMOTE_FAULT_BIT

#define MII_BMSR_REMOTE_FAULT_BIT   4

#include <zephyr/net/mii.h>

Remote fault bit position.

MII_ESTAT

#define MII_ESTAT   0xf

#include <zephyr/net/mii.h>

Extended Status Register.

MII_ESTAT_1000BASE_T_FULL

#define MII_ESTAT_1000BASE_T_FULL   BIT(13)

#include <zephyr/net/mii.h>

1000BASE-T full-duplex capable

MII_ESTAT_1000BASE_T_HALF

#define MII_ESTAT_1000BASE_T_HALF   BIT(12)

#include <zephyr/net/mii.h>

1000BASE-T half-duplex capable

MII_ESTAT_1000BASE_X_FULL

#define MII_ESTAT_1000BASE_X_FULL   BIT(15)

#include <zephyr/net/mii.h>

1000BASE-X full-duplex capable

MII_ESTAT_1000BASE_X_HALF

#define MII_ESTAT_1000BASE_X_HALF   BIT(14)

#include <zephyr/net/mii.h>

1000BASE-X half-duplex capable

MII_MMD_AADR

#define MII_MMD_AADR   0xe

#include <zephyr/net/mii.h>

MMD Access Address Data Register.

MII_MMD_ACR

#define MII_MMD_ACR   0xd

#include <zephyr/net/mii.h>

MMD Access Control Register.

MII_MMD_ACR_ADDR

#define MII_MMD_ACR_ADDR   (0x00 << 14)

#include <zephyr/net/mii.h>

Address.

MII_MMD_ACR_DATA_NO_POS_INC

#define MII_MMD_ACR_DATA_NO_POS_INC   (0x01 << 14)

#include <zephyr/net/mii.h>

Data, no post increment.

MII_MMD_ACR_DATA_RW_POS_INC

#define MII_MMD_ACR_DATA_RW_POS_INC   (0x10 << 14)

#include <zephyr/net/mii.h>

Data, post increment on reads and writes.

MII_MMD_ACR_DATA_W_POS_INC

#define MII_MMD_ACR_DATA_W_POS_INC   (0x11 << 14)

#include <zephyr/net/mii.h>

Data, post increment on writes only.

MII_MMD_ACR_DEVAD_MASK

#define MII_MMD_ACR_DEVAD_MASK   (0x1F << 0)

#include <zephyr/net/mii.h>

DEVAD Mask.

MII_PHYID1R

#define MII_PHYID1R   0x2

#include <zephyr/net/mii.h>

PHY ID 1 Register.

MII_PHYID2R

#define MII_PHYID2R   0x3

#include <zephyr/net/mii.h>

PHY ID 2 Register.