Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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gd32f4xx.h
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1/*
2 * Copyright (c) 2022 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
9
10#include "gd32-common.h"
11
17#define GD32_AHB1RST_OFFSET 0x10U
18#define GD32_AHB2RST_OFFSET 0x14U
19#define GD32_AHB3RST_OFFSET 0x18U
20#define GD32_APB1RST_OFFSET 0x20U
21#define GD32_APB2RST_OFFSET 0x24U
22#define GD32_ADDAPB1RST_OFFSET 0xE0U
23
31/* AHB1 peripherals */
32#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U)
33#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U)
34#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U)
35#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U)
36#define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U)
37#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U)
38#define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U)
39#define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U)
40#define GD32_RESET_GPIOI GD32_RESET_CONFIG(AHB1RST, 8U)
41#define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 12U)
42#define GD32_RESET_BKPSRAM GD32_RESET_CONFIG(AHB1RST, 18U)
43#define GD32_RESET_TCMSRAM GD32_RESET_CONFIG(AHB1RST, 20U)
44#define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHB1RST, 21U)
45#define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHB1RST, 22U)
46#define GD32_RESET_IPA GD32_RESET_CONFIG(AHB1RST, 23U)
47#define GD32_RESET_ENET GD32_RESET_CONFIG(AHB1RST, 25U)
48#define GD32_RESET_ENETTX GD32_RESET_CONFIG(AHB1RST, 26U)
49#define GD32_RESET_ENETRX GD32_RESET_CONFIG(AHB1RST, 27U)
50#define GD32_RESET_ENETPTP GD32_RESET_CONFIG(AHB1RST, 28U)
51#define GD32_RESET_USBHS GD32_RESET_CONFIG(AHB1RST, 29U)
52#define GD32_RESET_USBHSULPI GD32_RESET_CONFIG(AHB1RST, 30U)
53
54/* AHB2 peripherals */
55#define GD32_RESET_DCI GD32_RESET_CONFIG(AHB2RST, 0U)
56#define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 6U)
57#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHB2RST, 7U)
58
59/* AHB3 peripherals */
60#define GD32_RESET_EXMC GD32_RESET_CONFIG(AHB3RST, 0U)
61
62/* APB1 peripherals */
63#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
64#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
65#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
66#define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U)
67#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
68#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
69#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U)
70#define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U)
71#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
72#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
73#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
74#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
75#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
76#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
77#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
78#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
79#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
80#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
81#define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 23U)
82#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
83#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
84#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
85#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
86#define GD32_RESET_UART6 GD32_RESET_CONFIG(APB1RST, 30U)
87#define GD32_RESET_UART7 GD32_RESET_CONFIG(APB1RST, 31U)
88#define GD32_RESET_RTC GD32_RESET_CONFIG(BDCTL, 15U)
89
90/* APB2 peripherals */
91#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 0U)
92#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 1U)
93#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 4U)
94#define GD32_RESET_USART5 GD32_RESET_CONFIG(APB2RST, 5U)
95#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 8U)
96#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 9U)
97#define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 10U)
98#define GD32_RESET_SDIO GD32_RESET_CONFIG(APB2RST, 11U)
99#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
100#define GD32_RESET_SPI3 GD32_RESET_CONFIG(APB2RST, 13U)
101#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 14U)
102#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 16U)
103#define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 17U)
104#define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 18U)
105#define GD32_RESET_SPI4 GD32_RESET_CONFIG(APB2RST, 20U)
106#define GD32_RESET_SPI5 GD32_RESET_CONFIG(APB2RST, 21U)
107#define GD32_RESET_TLI GD32_RESET_CONFIG(APB2RST, 26U)
108
109/* APB1 additional peripherals */
110#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
111#define GD32_RESET_IREF GD32_RESET_CONFIG(ADDAPB1RST, 31U)
112
115#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ */