Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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gd32a50x.h
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/*
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* Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
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#include "
gd32-common.h
"
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#define GD32_AHBRST_OFFSET 0x28U
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#define GD32_APB1RST_OFFSET 0x10U
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#define GD32_APB2RST_OFFSET 0x0CU
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/* AHB peripherals */
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#define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHBRST, 0U)
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#define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHBRST, 1U)
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#define GD32_RESET_SRAMSP GD32_RESET_CONFIG(AHBRST, 2U)
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#define GD32_RESET_DMAMUX GD32_RESET_CONFIG(AHBRST, 3U)
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#define GD32_RESET_FMCSP GD32_RESET_CONFIG(AHBRST, 4U)
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#define GD32_RESET_CRC GD32_RESET_CONFIG(AHBRST, 6U)
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#define GD32_RESET_MFCOM GD32_RESET_CONFIG(AHBRST, 14U)
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#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
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#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U)
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#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U)
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#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U)
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#define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHBRST, 21U)
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#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U)
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/* APB1 peripherals */
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#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
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#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
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#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
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#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
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#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
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#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
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#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
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#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
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#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
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#define GD32_RESET_BKP GD32_RESET_CONFIG(APB1RST, 26U)
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#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
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#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
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/* APB2 peripherals */
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#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 0U)
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#define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 1U)
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#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
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#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
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#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
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#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
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#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U)
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#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
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#define GD32_RESET_TIMER19 GD32_RESET_CONFIG(APB2RST, 20U)
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#define GD32_RESET_TIMER20 GD32_RESET_CONFIG(APB2RST, 21U)
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#define GD32_RESET_TRIGSEL GD32_RESET_CONFIG(APB2RST, 29U)
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#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB2RST, 30U)
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#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB2RST, 31U)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ */
gd32-common.h
zephyr
dt-bindings
reset
gd32a50x.h
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