Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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esp-xtensa-intmux.h
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0
/* WiFi MAC, level */
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#define WIFI_MAC_NMI_SOURCE 1
/* WiFi MAC, NMI, use if MAC needs fix in NMI */
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#define WIFI_BB_INTR_SOURCE 2
/* WiFi BB, level, we can do some calibration */
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#define BT_MAC_INTR_SOURCE 3
/* will be cancelled */
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#define BT_BB_INTR_SOURCE 4
/* BB, level */
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#define BT_BB_NMI_SOURCE 5
/* BT BB, NMI, use if BB have bug to fix in NMI */
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#define RWBT_INTR_SOURCE 6
/* RWBT, level */
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#define RWBLE_INTR_SOURCE 7
/* RWBLE, level */
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#define RWBT_NMI_SOURCE 8
/* RWBT, NMI, use if RWBT has bug to fix in NMI */
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#define RWBLE_NMI_SOURCE 9
/* RWBLE, NMI, use if RWBT has bug to fix in NMI */
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#define SLC0_INTR_SOURCE 10
/* SLC0, level */
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#define SLC1_INTR_SOURCE 11
/* SLC1, level */
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#define UHCI0_INTR_SOURCE 12
/* UHCI0, level */
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#define UHCI1_INTR_SOURCE 13
/* UHCI1, level */
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#define TG0_T0_LEVEL_INTR_SOURCE 14
/* TIMER_GROUP0, TIMER0, level */
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#define TG0_T1_LEVEL_INTR_SOURCE 15
/* TIMER_GROUP0, TIMER1, level */
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#define TG0_WDT_LEVEL_INTR_SOURCE 16
/* TIMER_GROUP0, WATCHDOG, level */
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#define TG0_LACT_LEVEL_INTR_SOURCE 17
/* TIMER_GROUP0, LACT, level */
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#define TG1_T0_LEVEL_INTR_SOURCE 18
/* TIMER_GROUP1, TIMER0, level */
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#define TG1_T1_LEVEL_INTR_SOURCE 19
/* TIMER_GROUP1, TIMER1, level */
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#define TG1_WDT_LEVEL_INTR_SOURCE 20
/* TIMER_GROUP1, WATCHDOG, level */
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#define TG1_LACT_LEVEL_INTR_SOURCE 21
/* TIMER_GROUP1, LACT, level */
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#define GPIO_INTR_SOURCE 22
/* interrupt of GPIO, level */
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#define GPIO_NMI_SOURCE 23
/* interrupt of GPIO, NMI */
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#define FROM_CPU_INTR0_SOURCE 24
/* int0 from a CPU, level */
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#define FROM_CPU_INTR1_SOURCE 25
/* int1 from a CPU, level */
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#define FROM_CPU_INTR2_SOURCE 26
/* int2 from a CPU, level, for DPORT Access */
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#define FROM_CPU_INTR3_SOURCE 27
/* int3 from a CPU, level, for DPORT Access */
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#define SPI0_INTR_SOURCE 28
/* SPI0, level, for $ Access, do not use this */
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#define SPI1_INTR_SOURCE 29
/* SPI1, level, flash r/w, do not use this */
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#define SPI2_INTR_SOURCE 30
/* SPI2, level */
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#define SPI3_INTR_SOURCE 31
/* SPI3, level */
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#define I2S0_INTR_SOURCE 32
/* I2S0, level */
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#define I2S1_INTR_SOURCE 33
/* I2S1, level */
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#define UART0_INTR_SOURCE 34
/* UART0, level */
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#define UART1_INTR_SOURCE 35
/* UART1, level */
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#define UART2_INTR_SOURCE 36
/* UART2, level */
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#define SDIO_HOST_INTR_SOURCE 37
/* SD/SDIO/MMC HOST, level */
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#define ETH_MAC_INTR_SOURCE 38
/* ethernet mac, level */
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#define PWM0_INTR_SOURCE 39
/* PWM0, level, Reserved */
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#define PWM1_INTR_SOURCE 40
/* PWM1, level, Reserved */
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#define PWM2_INTR_SOURCE 41
/* PWM2, level */
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#define PWM3_INTR_SOURCE 42
/* PWM3, level */
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#define LEDC_INTR_SOURCE 43
/* LED PWM, level */
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#define EFUSE_INTR_SOURCE 44
/* efuse, level, not likely to use */
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#define TWAI_INTR_SOURCE 45
/* twai, level */
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#define CAN_INTR_SOURCE TWAI_INTR_SOURCE
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#define RTC_CORE_INTR_SOURCE 46
/* rtc core, level, include rtc watchdog */
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#define RMT_INTR_SOURCE 47
/* remote controller, level */
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#define PCNT_INTR_SOURCE 48
/* pulse count, level */
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#define I2C_EXT0_INTR_SOURCE 49
/* I2C controller1, level */
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#define I2C_EXT1_INTR_SOURCE 50
/* I2C controller0, level */
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#define RSA_INTR_SOURCE 51
/* RSA accelerator, level */
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#define SPI1_DMA_INTR_SOURCE 52
/* SPI1 DMA, for flash r/w, do not use it */
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#define SPI2_DMA_INTR_SOURCE 53
/* SPI2 DMA, level */
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#define SPI3_DMA_INTR_SOURCE 54
/* interrupt of SPI3 DMA, level */
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#define WDT_INTR_SOURCE 55
/* will be cancelled */
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#define TIMER1_INTR_SOURCE 56
/* will be cancelled */
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#define TIMER2_INTR_SOURCE 57
/* will be cancelled */
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#define TG0_T0_EDGE_INTR_SOURCE 58
/* TIMER_GROUP0, TIMER0, EDGE */
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#define TG0_T1_EDGE_INTR_SOURCE 59
/* TIMER_GROUP0, TIMER1, EDGE */
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#define TG0_WDT_EDGE_INTR_SOURCE 60
/* TIMER_GROUP0, WATCH DOG, EDGE */
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#define TG0_LACT_EDGE_INTR_SOURCE 61
/* TIMER_GROUP0, LACT, EDGE */
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#define TG1_T0_EDGE_INTR_SOURCE 62
/* TIMER_GROUP1, TIMER0, EDGE */
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#define TG1_T1_EDGE_INTR_SOURCE 63
/* TIMER_GROUP1, TIMER1, EDGE */
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#define TG1_WDT_EDGE_INTR_SOURCE 64
/* TIMER_GROUP1, WATCHDOG, EDGE */
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#define TG1_LACT_EDGE_INTR_SOURCE 65
/* TIMER_GROUP0, LACT, EDGE */
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#define MMU_IA_INTR_SOURCE 66
/* MMU Invalid Access, LEVEL */
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#define MPU_IA_INTR_SOURCE 67
/* MPU Invalid Access, LEVEL */
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#define CACHE_IA_INTR_SOURCE 68
/* Cache Invalid Access, LEVEL */
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#define MAX_INTR_SOURCE 69
/* total number of interrupt sources */
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/* For Xtensa architecture, zero will allocate low/medium
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* levels of priority (ESP_INTR_FLAG_LOWMED)
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*/
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#define IRQ_DEFAULT_PRIORITY 0
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#define ESP_INTR_FLAG_SHARED (1<<8)
/* Interrupt can be shared between ISRs */
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#endif
zephyr
dt-bindings
interrupt-controller
esp-xtensa-intmux.h
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