Zephyr API Documentation
4.0.0-rc3
A Scalable Open Source RTOS
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esp-esp32c6-intmux.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0
/* interrupt of WiFi MAC, level*/
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#define WIFI_MAC_NMI_SOURCE 1
/* interrupt of WiFi MAC, NMI*/
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#define WIFI_PWR_INTR_SOURCE 2
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#define WIFI_BB_INTR_SOURCE 3
/* interrupt of WiFi BB, level*/
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#define BT_MAC_INTR_SOURCE 4
/* will be cancelled*/
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#define BT_BB_INTR_SOURCE 5
/* interrupt of BT BB, level*/
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#define BT_BB_NMI_SOURCE 6
/* interrupt of BT BB, NMI*/
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#define LP_TIMER_INTR_SOURCE 7
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#define COEX_INTR_SOURCE 8
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#define BLE_TIMER_INTR_SOURCE 9
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#define BLE_SEC_INTR_SOURCE 10
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#define I2C_MASTER_SOURCE 11
/* interrupt of I2C Master, level*/
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#define ZB_MAC_SOURCE 12
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#define PMU_INTR_SOURCE 13
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#define EFUSE_INTR_SOURCE 14
/* interrupt of efuse, level, not likely to use*/
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#define LP_RTC_TIMER_INTR_SOURCE 15
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#define LP_UART_INTR_SOURCE 16
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#define LP_I2C_INTR_SOURCE 17
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#define LP_WDT_INTR_SOURCE 18
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#define LP_PERI_TIMEOUT_INTR_SOURCE 19
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#define LP_APM_M0_INTR_SOURCE 20
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#define LP_APM_M1_INTR_SOURCE 21
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#define FROM_CPU_INTR0_SOURCE 22
/* interrupt0 generated from a CPU, level*/
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#define FROM_CPU_INTR1_SOURCE 23
/* interrupt1 generated from a CPU, level*/
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#define FROM_CPU_INTR2_SOURCE 24
/* interrupt2 generated from a CPU, level*/
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#define FROM_CPU_INTR3_SOURCE 25
/* interrupt3 generated from a CPU, level*/
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#define ASSIST_DEBUG_INTR_SOURCE 26
/* interrupt of Assist debug module, LEVEL*/
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#define TRACE_INTR_SOURCE 27
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#define CACHE_INTR_SOURCE 28
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#define CPU_PERI_TIMEOUT_INTR_SOURCE 29
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#define GPIO_INTR_SOURCE 30
/* interrupt of GPIO, level*/
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#define GPIO_NMI_SOURCE 31
/* interrupt of GPIO, NMI*/
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#define PAU_INTR_SOURCE 32
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#define HP_PERI_TIMEOUT_INTR_SOURCE 33
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#define MODEM_PERI_TIMEOUT_INTR_SOURCE 34
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#define HP_APM_M0_INTR_SOURCE 35
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#define HP_APM_M1_INTR_SOURCE 36
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#define HP_APM_M2_INTR_SOURCE 37
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#define HP_APM_M3_INTR_SOURCE 38
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#define LP_APM0_INTR_SOURCE 39
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#define MSPI_INTR_SOURCE 40
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#define I2S1_INTR_SOURCE 41
/* interrupt of I2S1, level*/
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#define UHCI0_INTR_SOURCE 42
/* interrupt of UHCI0, level*/
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#define UART0_INTR_SOURCE 43
/* interrupt of UART0, level*/
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#define UART1_INTR_SOURCE 44
/* interrupt of UART1, level*/
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#define LEDC_INTR_SOURCE 45
/* interrupt of LED PWM, level*/
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#define TWAI0_INTR_SOURCE 46
/* interrupt of can0, level*/
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#define TWAI1_INTR_SOURCE 47
/* interrupt of can1, level*/
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#define USB_SERIAL_JTAG_INTR_SOURCE 48
/* interrupt of USB, level*/
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#define RMT_INTR_SOURCE 49
/* interrupt of remote controller, level*/
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#define I2C_EXT0_INTR_SOURCE 50
/* interrupt of I2C controller1, level*/
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#define TG0_T0_LEVEL_INTR_SOURCE 51
/* interrupt of TIMER_GROUP0, TIMER0, level*/
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#define TG0_T1_LEVEL_INTR_SOURCE 52
/* interrupt of TIMER_GROUP0, TIMER1, level*/
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#define TG0_WDT_LEVEL_INTR_SOURCE 53
/* interrupt of TIMER_GROUP0, WATCH DOG, level*/
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#define TG1_T0_LEVEL_INTR_SOURCE 54
/* interrupt of TIMER_GROUP1, TIMER0, level*/
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#define TG1_T1_LEVEL_INTR_SOURCE 55
/* interrupt of TIMER_GROUP1, TIMER1, level*/
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#define TG1_WDT_LEVEL_INTR_SOURCE 56
/* interrupt of TIMER_GROUP1, WATCHDOG, level*/
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 57
/* interrupt of system timer 0, EDGE*/
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 58
/* interrupt of system timer 1, EDGE*/
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 59
/* interrupt of system timer 2, EDGE*/
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#define APB_ADC_INTR_SOURCE 60
/* interrupt of APB ADC, LEVEL*/
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#define MCPWM0_INTR_SOURCE 61
/* interrupt of MCPWM0, LEVEL*/
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#define PCNT_INTR_SOURCE 62
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#define PARL_IO_INTR_SOURCE 63
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#define SLC0_INTR_SOURCE 64
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#define SLC_INTR_SOURCE 65
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#define DMA_IN_CH0_INTR_SOURCE 66
/* interrupt of general DMA IN channel 0, LEVEL*/
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#define DMA_IN_CH1_INTR_SOURCE 67
/* interrupt of general DMA IN channel 1, LEVEL*/
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#define DMA_IN_CH2_INTR_SOURCE 68
/* interrupt of general DMA IN channel 2, LEVEL*/
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#define DMA_OUT_CH0_INTR_SOURCE 69
/* interrupt of general DMA OUT channel 0, LEVEL*/
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#define DMA_OUT_CH1_INTR_SOURCE 70
/* interrupt of general DMA OUT channel 1, LEVEL*/
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#define DMA_OUT_CH2_INTR_SOURCE 71
/* interrupt of general DMA OUT channel 2, LEVEL*/
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#define GSPI2_INTR_SOURCE 72
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#define AES_INTR_SOURCE 73
/* interrupt of AES accelerator, level*/
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#define SHA_INTR_SOURCE 74
/* interrupt of SHA accelerator, level*/
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#define RSA_INTR_SOURCE 75
/* interrupt of RSA accelerator, level*/
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#define ECC_INTR_SOURCE 76
/* interrupt of ECC accelerator, level*/
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#define MAX_INTR_SOURCE 77
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/* RISC-V supports priority values from 1 (lowest) to 15.
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* As interrupt controller for Xtensa and RISC-V is shared, this is
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* set to an intermediate and compatible value.
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*/
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#define IRQ_DEFAULT_PRIORITY 3
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#define ESP_INTR_FLAG_SHARED (1<<8)
/* Interrupt can be shared between ISRs */
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ */
zephyr
dt-bindings
interrupt-controller
esp-esp32c6-intmux.h
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