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4.2.0-rc3
A Scalable Open Source RTOS
4.2.0-rc3
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dma_mcux_lpc.h
Go to the documentation of this file.
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_
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/*
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* LPC DMA engine channel hardware trigger attributes.
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* These attributes can be set to the "dma_slot" field
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* in a dma_config structure to configure a channel for
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* hardware triggering.
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*/
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/* Peripheral request enable. When set, the peripheral
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* request line associated with this channel is used to pace DMA transfers.
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*/
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#define LPC_DMA_PERIPH_REQ_EN BIT(0)
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/* Hardware trigger enable. When set, the hardware trigger connected to this
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* channel via INPUTMUX can be used to trigger a transfer
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*/
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#define LPC_DMA_HWTRIG_EN BIT(1)
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/* HW trigger polarity. When this bit is set, the trigger will be active
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* high or rising edge triggered, based on TRIG_TYPE selection
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*/
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#define LPC_DMA_TRIGPOL_HIGH_RISING BIT(2)
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/* HW trigger type. When this bit is set, the trigger will be level triggered.
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* When it is cleared, the hardware trigger will be edge triggered.
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*/
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#define LPC_DMA_TRIGTYPE_LEVEL BIT(3)
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/* HW trigger burst mode. When set, the hardware trigger will cause a burst
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* transfer to occur, the length of which is determined by BURST_POWER.
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* When cleared, a single transfer (of the width selected by XFERCFG register)
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* will occur.
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*/
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#define LPC_DMA_TRIGBURST BIT(4)
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/* HW trigger burst power. Note that due to the size limit of the dma_slot
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* field, the maximum transfer burst possible is 128. The hardware supports
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* up to 1024 transfers in BURSTPOWER. The value set here will result in
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* 2^BURSTPOWER transfers occurring. So for BURSTPOWER=3, 8 transfers would
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* occur.
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*/
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#define LPC_DMA_BURSTPOWER(pwr) (((pwr) & 0x7) << 5)
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/* Used by driver to extract burstpower setting */
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#define LPC_DMA_GET_BURSTPOWER(slot) (((slot) & 0xE0) >> 5)
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#endif
/* ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_MCUX_LPC_H_ */
zephyr
drivers
dma
dma_mcux_lpc.h
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