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ch32v00x-pinctrl.h
Go to the documentation of this file.
1
/*
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* Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __CH32V00X_PINCTRL_H__
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#define __CH32V00X_PINCTRL_H__
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#define CH32V00X_PINMUX_PORT_PA 0
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#define CH32V00X_PINMUX_PORT_PB 1
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#define CH32V00X_PINMUX_PORT_PC 2
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#define CH32V00X_PINMUX_PORT_PD 3
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/* Starting bit for the remap field in PCFR1 */
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#define CH32V00X_PINMUX_SPI1_RM 0
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#define CH32V00X_PINMUX_I2C1_RM 3
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#define CH32V00X_PINMUX_USART1_RM 6
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#define CH32V00X_PINMUX_TIM1_RM 10
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#define CH32V00X_PINMUX_TIM2_RM 14
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#define CH32V00X_PINMUX_PA1PA2_RM 17
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#define CH32V00X_PINMUX_ADC_DTR_GINJ_RM 18
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#define CH32V00X_PINMUX_ADC_DTR_GREG_RM 19
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#define CH32V00X_PINMUX_USART2_RM 20
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/* Port number with 0-3 */
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#define CH32V00X_PINCTRL_PORT_SHIFT 0
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#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0)
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/* Pin number 0-7 */
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#define CH32V00X_PINCTRL_PIN_SHIFT 2
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#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2)
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/* Base remap bit 0-31 */
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#define CH32V00X_PINCTRL_BASE_SHIFT 5
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#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5)
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/* Function remapping ID 0-7 */
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#define CH32V00X_PINCTRL_RM_SHIFT 10
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#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10)
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#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \
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((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \
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(pin << CH32V00X_PINCTRL_PIN_SHIFT) | \
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(CH32V00X_PINMUX_##rm##_RM << CH32V00X_PINCTRL_BASE_SHIFT) | \
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(remapping << CH32V00X_PINCTRL_RM_SHIFT))
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#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \
…
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#define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0)
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#define TIM1_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 1)
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#define TIM1_ETR_PD4_2 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 2)
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#define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3)
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#define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0)
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#define TIM1_CH1_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 1)
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#define TIM1_CH1_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 2)
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#define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3)
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#define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0)
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#define TIM1_CH2_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 1)
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#define TIM1_CH2_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 2)
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#define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3)
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#define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0)
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#define TIM1_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 1)
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#define TIM1_CH3_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2)
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#define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3)
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#define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0)
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#define TIM1_CH4_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 1)
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#define TIM1_CH4_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2)
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#define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3)
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#define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0)
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#define TIM1_BKIN_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 1)
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#define TIM1_BKIN_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 2)
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#define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3)
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#define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0)
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#define TIM1_CH1N_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1)
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#define TIM1_CH1N_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 2)
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#define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3)
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#define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0)
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#define TIM1_CH2N_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1)
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#define TIM1_CH2N_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 2)
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#define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3)
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#define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0)
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#define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1)
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#define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2)
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#define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3)
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#define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
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#define TIM2_ETR_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1)
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#define TIM2_ETR_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
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#define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
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#define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
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#define TIM2_CH1_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 1)
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#define TIM2_CH1_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
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#define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
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#define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0)
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#define TIM2_CH2_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 1)
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#define TIM2_CH2_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 2)
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#define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3)
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#define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0)
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#define TIM2_CH3_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 1)
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#define TIM2_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 2)
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#define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3)
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#define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0)
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#define TIM2_CH4_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
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#define TIM2_CH4_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 2)
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#define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3)
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#define USART1_CK_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 0)
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#define USART1_CK_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 1)
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#define USART1_CK_PD7_2 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 2)
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#define USART1_CK_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 3)
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#define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0)
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#define USART1_TX_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 1)
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#define USART1_TX_PD6_2 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 2)
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#define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3)
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#define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0)
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#define USART1_RX_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 1)
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#define USART1_RX_PD5_2 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 2)
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#define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3)
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#define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0)
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#define USART1_CTS_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 1)
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#define USART1_CTS_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 2)
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#define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3)
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#define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0)
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#define USART1_RTS_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 1)
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#define USART1_RTS_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 2)
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#define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3)
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#define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0)
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#define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1)
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#define USART2_TX_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, USART2, 2)
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#define USART2_TX_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, USART2, 3)
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#define USART2_TX_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, USART2, 4)
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#define USART2_TX_PC4_5 CH32V00X_PINMUX_DEFINE(PC, 4, USART2, 5)
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#define USART2_TX_PA6_6 CH32V00X_PINMUX_DEFINE(PA, 6, USART2, 6)
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#define USART2_RX_PB3_0 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 0)
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#define USART2_RX_PA5_1 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 1)
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#define USART2_RX_PA3_2 CH32V00X_PINMUX_DEFINE(PA, 3, USART2, 2)
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#define USART2_RX_PD3_3 CH32V00X_PINMUX_DEFINE(PD, 3, USART2, 3)
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#define USART2_RX_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, USART2, 4)
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#define USART2_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART2, 5)
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#define USART2_RX_PA5_6 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 6)
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#define USART2_CTS_PA4_0 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 0)
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#define USART2_CTS_PA7_1 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 1)
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#define USART2_CTS_PA0_2 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 2)
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#define USART2_CTS_PA0_3 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 3)
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#define USART2_CTS_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, USART2, 4)
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#define USART2_CTS_PA4_5 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 5)
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#define USART2_CTS_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 6)
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#define USART2_RTS_PA5_0 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 0)
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#define USART2_RTS_PB3_1 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 1)
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#define USART2_RTS_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 2)
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#define USART2_RTS_PA1_3 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 3)
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#define USART2_RTS_PA1_4 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 4)
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#define USART2_RTS_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 5)
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#define USART2_RTS_PB3_6 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 6)
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#define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0)
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#define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1)
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#define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0)
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#define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1)
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#define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0)
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#define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1)
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#define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0)
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#define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1)
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#define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0)
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#define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1)
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#define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2)
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#define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0)
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#define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1)
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#define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2)
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#endif
/* __CH32V00X_PINCTRL_H__ */
zephyr
dt-bindings
pinctrl
ch32v00x-pinctrl.h
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1.12.0
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