Zephyr API Documentation 4.2.99
A Scalable Open Source RTOS
 4.2.99
ch32v00x-pinctrl.h
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1/*
2 * Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef __CH32V00X_PINCTRL_H__
8#define __CH32V00X_PINCTRL_H__
9
10#define CH32V00X_PINMUX_PORT_PA 0
11#define CH32V00X_PINMUX_PORT_PB 1
12#define CH32V00X_PINMUX_PORT_PC 2
13#define CH32V00X_PINMUX_PORT_PD 3
14
15/* Starting bit for the remap field in PCFR1 */
16#define CH32V00X_PINMUX_SPI1_RM 0
17#define CH32V00X_PINMUX_I2C1_RM 3
18#define CH32V00X_PINMUX_USART1_RM 6
19#define CH32V00X_PINMUX_TIM1_RM 10
20#define CH32V00X_PINMUX_TIM2_RM 14
21#define CH32V00X_PINMUX_PA1PA2_RM 17
22#define CH32V00X_PINMUX_ADC_DTR_GINJ_RM 18
23#define CH32V00X_PINMUX_ADC_DTR_GREG_RM 19
24#define CH32V00X_PINMUX_USART2_RM 20
25
26/* Port number with 0-3 */
27#define CH32V00X_PINCTRL_PORT_SHIFT 0
28#define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0)
29/* Pin number 0-7 */
30#define CH32V00X_PINCTRL_PIN_SHIFT 2
31#define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2)
32/* Base remap bit 0-31 */
33#define CH32V00X_PINCTRL_BASE_SHIFT 5
34#define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5)
35/* Function remapping ID 0-7 */
36#define CH32V00X_PINCTRL_RM_SHIFT 10
37#define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10)
38
39#define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \
40 ((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \
41 (pin << CH32V00X_PINCTRL_PIN_SHIFT) | \
42 (CH32V00X_PINMUX_##rm##_RM << CH32V00X_PINCTRL_BASE_SHIFT) | \
43 (remapping << CH32V00X_PINCTRL_RM_SHIFT))
44
45#define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0)
46#define TIM1_ETR_PD4_1 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 1)
47#define TIM1_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 2)
48#define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3)
49#define TIM1_ETR_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 4)
50#define TIM1_ETR_PD4_5 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 5)
51#define TIM1_ETR_PD4_6 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 6)
52#define TIM1_ETR_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 7)
53#define TIM1_ETR_PB4_8 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 8)
54#define TIM1_ETR_PB4_9 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 9)
55#define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0)
56#define TIM1_CH1_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 1)
57#define TIM1_CH1_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 2)
58#define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3)
59#define TIM1_CH1_PA3_4 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 4)
60#define TIM1_CH1_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 5)
61#define TIM1_CH1_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 6)
62#define TIM1_CH1_PC4_7 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 7)
63#define TIM1_CH1_PC4_8 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 8)
64#define TIM1_CH1_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 9)
65#define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0)
66#define TIM1_CH2_PA1_1 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 1)
67#define TIM1_CH2_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 2)
68#define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3)
69#define TIM1_CH2_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 4)
70#define TIM1_CH2_PB0_5 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 5)
71#define TIM1_CH2_PB0_6 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 6)
72#define TIM1_CH2_PC5_7 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 7)
73#define TIM1_CH2_PC5_8 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 8)
74#define TIM1_CH2_PA1_9 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 9)
75#define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0)
76#define TIM1_CH3_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1)
77#define TIM1_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 2)
78#define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3)
79#define TIM1_CH3_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 4)
80#define TIM1_CH3_PC3_5 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 5)
81#define TIM1_CH3_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 6)
82#define TIM1_CH3_PC6_7 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 7)
83#define TIM1_CH3_PC6_8 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 8)
84#define TIM1_CH3_PA2_9 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 9)
85#define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0)
86#define TIM1_CH4_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1)
87#define TIM1_CH4_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 2)
88#define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3)
89#define TIM1_CH4_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 4)
90#define TIM1_CH4_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 5)
91#define TIM1_CH4_PB2_6 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 6)
92#define TIM1_CH4_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 7)
93#define TIM1_CH4_PC7_8 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 8)
94#define TIM1_CH4_PA3_9 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 9)
95#define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0)
96#define TIM1_BKIN_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 1)
97#define TIM1_BKIN_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 2)
98#define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3)
99#define TIM1_BKIN_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 4)
100#define TIM1_BKIN_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 5)
101#define TIM1_BKIN_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, TIM1, 6)
102#define TIM1_BKIN_PB2_7 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 7)
103#define TIM1_BKIN_PB2_8 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 8)
104#define TIM1_BKIN_PB2_9 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 9)
105#define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0)
106#define TIM1_CH1N_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 1)
107#define TIM1_CH1N_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2)
108#define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3)
109#define TIM1_CH1N_PA0_4 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 4)
110#define TIM1_CH1N_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 5)
111#define TIM1_CH1N_PA0_6 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 6)
112#define TIM1_CH1N_PC0_7 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 7)
113#define TIM1_CH1N_PA3_8 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 8)
114#define TIM1_CH1N_PC0_9 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 9)
115#define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0)
116#define TIM1_CH2N_PA2_1 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 1)
117#define TIM1_CH2N_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2)
118#define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3)
119#define TIM1_CH2N_PA2_4 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 4)
120#define TIM1_CH2N_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 5)
121#define TIM1_CH2N_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 6)
122#define TIM1_CH2N_PC1_7 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 7)
123#define TIM1_CH2N_PB0_8 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 8)
124#define TIM1_CH2N_PC1_9 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 9)
125#define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0)
126#define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1)
127#define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2)
128#define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3)
129#define TIM1_CH3N_PD0_4 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 4)
130#define TIM1_CH3N_PD0_5 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 5)
131#define TIM1_CH3N_PD0_6 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 6)
132#define TIM1_CH3N_PC2_7 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 7)
133#define TIM1_CH3N_PB1_8 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 8)
134#define TIM1_CH3N_PC2_9 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 9)
135
136#define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
137#define TIM2_ETR_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
138#define TIM2_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
139#define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
140#define TIM2_ETR_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
141#define TIM2_ETR_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
142#define TIM2_ETR_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
143#define TIM2_ETR_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
144#define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
145#define TIM2_CH1_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
146#define TIM2_CH1_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
147#define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
148#define TIM2_CH1_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
149#define TIM2_CH1_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
150#define TIM2_CH1_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
151#define TIM2_CH1_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
152#define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0)
153#define TIM2_CH2_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 1)
154#define TIM2_CH2_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 2)
155/* CH32V007 specific remap */
156#define TIM2_CH2_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, TIM2, 2)
157#define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3)
158#define TIM2_CH2_PC1_4 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 4)
159#define TIM2_CH2_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 5)
160#define TIM2_CH2_PA1_6 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 6)
161#define TIM2_CH2_PD4_7 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 7)
162#define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0)
163#define TIM2_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 1)
164#define TIM2_CH3_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 2)
165#define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3)
166#define TIM2_CH3_PC3_4 CH32V00X_PINMUX_DEFINE(PC, 3, TIM2, 4)
167#define TIM2_CH3_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 5)
168#define TIM2_CH3_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 6)
169#define TIM2_CH3_PA2_7 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 7)
170#define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0)
171#define TIM2_CH4_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 1)
172#define TIM2_CH4_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
173#define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3)
174#define TIM2_CH4_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, TIM2, 4)
175#define TIM2_CH4_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 5)
176#define TIM2_CH4_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 6)
177#define TIM2_CH4_PA3_7 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 7)
178
179#define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0)
180#define USART1_TX_PD6_1 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 1)
181#define USART1_TX_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 2)
182#define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3)
183#define USART1_TX_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 4)
184#define USART1_TX_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 5)
185#define USART1_TX_PC5_6 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 6)
186#define USART1_TX_PB5_7 CH32V00X_PINMUX_DEFINE(PB, 5, USART1, 7)
187#define USART1_TX_PA0_8 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 8)
188#define USART1_TX_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 9)
189#define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0)
190#define USART1_RX_PD5_1 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 1)
191#define USART1_RX_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 2)
192#define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3)
193#define USART1_RX_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 4)
194#define USART1_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 5)
195#define USART1_RX_PC6_6 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 6)
196#define USART1_RX_PB6_7 CH32V00X_PINMUX_DEFINE(PB, 6, USART1, 7)
197#define USART1_RX_PA1_8 CH32V00X_PINMUX_DEFINE(PA, 1, USART1, 8)
198#define USART1_RX_PC4_9 CH32V00X_PINMUX_DEFINE(PC, 4, USART1, 9)
199#define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0)
200#define USART1_CTS_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 1)
201#define USART1_CTS_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 2)
202#define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3)
203#define USART1_CTS_PD7_4 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 4)
204#define USART1_CTS_PD7_5 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 5)
205#define USART1_CTS_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 6)
206#define USART1_CTS_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 7)
207#define USART1_CTS_PD2_8 CH32V00X_PINMUX_DEFINE(PD, 2, USART1, 8)
208#define USART1_CTS_PD5_9 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 9)
209#define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0)
210#define USART1_RTS_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 1)
211#define USART1_RTS_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 2)
212#define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3)
213#define USART1_RTS_PA5_4 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 4)
214#define USART1_RTS_PA5_5 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 5)
215#define USART1_RTS_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 6)
216#define USART1_RTS_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 7)
217#define USART1_RTS_PD3_8 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 8)
218#define USART1_RTS_PD4_9 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 9)
219
220#define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0)
221#define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1)
222#define USART2_TX_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, USART2, 2)
223#define USART2_TX_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, USART2, 3)
224#define USART2_TX_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, USART2, 4)
225#define USART2_TX_PC4_5 CH32V00X_PINMUX_DEFINE(PC, 4, USART2, 5)
226#define USART2_TX_PA6_6 CH32V00X_PINMUX_DEFINE(PA, 6, USART2, 6)
227#define USART2_RX_PB3_0 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 0)
228#define USART2_RX_PA5_1 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 1)
229#define USART2_RX_PA3_2 CH32V00X_PINMUX_DEFINE(PA, 3, USART2, 2)
230#define USART2_RX_PD3_3 CH32V00X_PINMUX_DEFINE(PD, 3, USART2, 3)
231#define USART2_RX_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, USART2, 4)
232#define USART2_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART2, 5)
233#define USART2_RX_PA5_6 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 6)
234#define USART2_CTS_PA4_0 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 0)
235#define USART2_CTS_PA7_1 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 1)
236#define USART2_CTS_PA0_2 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 2)
237#define USART2_CTS_PA0_3 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 3)
238#define USART2_CTS_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, USART2, 4)
239#define USART2_CTS_PA4_5 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 5)
240#define USART2_CTS_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 6)
241#define USART2_RTS_PA5_0 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 0)
242#define USART2_RTS_PB3_1 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 1)
243#define USART2_RTS_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 2)
244#define USART2_RTS_PA1_3 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 3)
245#define USART2_RTS_PA1_4 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 4)
246#define USART2_RTS_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 5)
247#define USART2_RTS_PB3_6 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 6)
248
249#define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0)
250#define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1)
251#define SPI1_NSS_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 2)
252#define SPI1_NSS_PB0_3 CH32V00X_PINMUX_DEFINE(PB, 0, SPI1, 3)
253#define SPI1_NSS_PD3_4 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 4)
254#define SPI1_NSS_PC1_5 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 5)
255#define SPI1_NSS_PC4_6 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 6)
256#define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0)
257#define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1)
258#define SPI1_SCK_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, SPI1, 2)
259#define SPI1_SCK_PB1_3 CH32V00X_PINMUX_DEFINE(PB, 1, SPI1, 3)
260#define SPI1_SCK_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, SPI1, 4)
261#define SPI1_SCK_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, SPI1, 5)
262#define SPI1_SCK_PB5_6 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 6)
263#define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0)
264#define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1)
265#define SPI1_MISO_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, SPI1, 2)
266#define SPI1_MISO_PB2_3 CH32V00X_PINMUX_DEFINE(PB, 2, SPI1, 3)
267#define SPI1_MISO_PD5_4 CH32V00X_PINMUX_DEFINE(PD, 5, SPI1, 4)
268#define SPI1_MISO_PB5_5 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 5)
269#define SPI1_MISO_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 6)
270#define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0)
271#define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1)
272#define SPI1_MOSI_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 2)
273#define SPI1_MOSI_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 3)
274#define SPI1_MOSI_PD6_4 CH32V00X_PINMUX_DEFINE(PD, 6, SPI1, 4)
275#define SPI1_MOSI_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, SPI1, 5)
276#define SPI1_MOSI_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, SPI1, 6)
277
278#define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0)
279#define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1)
280#define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2)
281#define I2C1_SCL_PB5_3 CH32V00X_PINMUX_DEFINE(PB, 5, I2C1, 3)
282#define I2C1_SCL_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, I2C1, 4)
283#define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0)
284#define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1)
285#define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2)
286/* CH32V007 specific remap */
287#define I2C1_SDA_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, I2C1, 2)
288#define I2C1_SDA_PB6_3 CH32V00X_PINMUX_DEFINE(PB, 6, I2C1, 3)
289#define I2C1_SDA_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 4)
290
291#endif /* __CH32V00X_PINCTRL_H__ */