13#ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_
14#define ZEPHYR_INCLUDE_SYS_BARRIER_H_
18#if defined(CONFIG_BARRIER_OPERATIONS_ARCH)
19# if defined(CONFIG_ARM)
20# include <zephyr/arch/arm/barrier.h>
21# elif defined(CONFIG_ARM64)
22# include <zephyr/arch/arm64/barrier.h>
24#elif defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
49#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
50 z_barrier_sync_synchronize();
62#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
63 z_barrier_dmem_fence_full();
81#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
82 z_barrier_dsync_fence_full();
100#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
101 z_barrier_isync_fence_full();
Compiler-builtin implementation of the memory barrier API.
static ALWAYS_INLINE void barrier_sync_synchronize(void)
Full/sequentially-consistent data memory barrier across cores.
Definition barrier.h:47
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition barrier.h:98
static ALWAYS_INLINE void barrier_dsync_fence_full(void)
Full/sequentially-consistent data synchronization barrier.
Definition barrier.h:79
static ALWAYS_INLINE void barrier_dmem_fence_full(void)
Full/sequentially-consistent data memory barrier.
Definition barrier.h:60