Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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ast10x0_reset.h
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/*
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* Copyright (c) 2022 Aspeed Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
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#define ASPEED_RESET_GRP_0_OFFSET (0)
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#define ASPEED_RESET_GRP_1_OFFSET (32)
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#define ASPEED_RESET_HACE (ASPEED_RESET_GRP_0_OFFSET + 4)
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#define ASPEED_RESET_USB (ASPEED_RESET_GRP_0_OFFSET + 3)
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#define ASPEED_RESET_SRAM (ASPEED_RESET_GRP_0_OFFSET + 0)
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#define ASPEED_RESET_UART4 (ASPEED_RESET_GRP_1_OFFSET + 31)
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#define ASPEED_RESET_UART3 (ASPEED_RESET_GRP_1_OFFSET + 30)
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#define ASPEED_RESET_UART2 (ASPEED_RESET_GRP_1_OFFSET + 29)
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#define ASPEED_RESET_UART1 (ASPEED_RESET_GRP_1_OFFSET + 28)
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#define ASPEED_RESET_JTAG_M0 (ASPEED_RESET_GRP_1_OFFSET + 26)
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#define ASPEED_RESET_ESPI (ASPEED_RESET_GRP_1_OFFSET + 25)
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#define ASPEED_RESET_ADC (ASPEED_RESET_GRP_1_OFFSET + 23)
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#define ASPEED_RESET_JTAG_M1 (ASPEED_RESET_GRP_1_OFFSET + 22)
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#define ASPEED_RESET_MAC (ASPEED_RESET_GRP_1_OFFSET + 20)
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#define ASPEED_RESET_I3C3 (ASPEED_RESET_GRP_1_OFFSET + 11)
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#define ASPEED_RESET_I3C2 (ASPEED_RESET_GRP_1_OFFSET + 10)
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#define ASPEED_RESET_I3C1 (ASPEED_RESET_GRP_1_OFFSET + 9)
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#define ASPEED_RESET_I3C0 (ASPEED_RESET_GRP_1_OFFSET + 8)
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#define ASPEED_RESET_I3C (ASPEED_RESET_GRP_1_OFFSET + 7)
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#define ASPEED_RESET_PWM_TACH (ASPEED_RESET_GRP_1_OFFSET + 5)
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#define ASPEED_RESET_PECI (ASPEED_RESET_GRP_1_OFFSET + 4)
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#define ASPEED_RESET_MII (ASPEED_RESET_GRP_1_OFFSET + 3)
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#define ASPEED_RESET_I2C (ASPEED_RESET_GRP_1_OFFSET + 2)
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#define ASPEED_RESET_LPC (ASPEED_RESET_GRP_1_OFFSET + 0)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ */
zephyr
dt-bindings
reset
ast10x0_reset.h
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