6#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
7#define ZEPHYR_INCLUDE_ARCH_XTENSA_XTENSA_IRQ_H_
12#include <xtensa/config/core-isa.h>
14#define CONFIG_GEN_IRQ_START_VECTOR 0
25static inline void z_xt_ints_on(
unsigned int mask)
29 __asm__
volatile(
"rsr.intenable %0" :
"=r"(val));
31 __asm__
volatile(
"wsr.intenable %0; rsync" : :
"r"(val));
33#if XCHAL_NUM_INTERRUPTS > 32
34static inline void z_xt_ints1_on(
unsigned int mask)
38 __asm__
volatile(
"rsr.intenable1 %0" :
"=r"(val));
40 __asm__
volatile(
"wsr.intenable1 %0; rsync" : :
"r"(val));
43#if XCHAL_NUM_INTERRUPTS > 64
44static inline void z_xt_ints2_on(
unsigned int mask)
48 __asm__
volatile(
"rsr.intenable2 %0" :
"=r"(val));
50 __asm__
volatile(
"wsr.intenable2 %0; rsync" : :
"r"(val));
53#if XCHAL_NUM_INTERRUPTS > 96
54static inline void z_xt_ints3_on(
unsigned int mask)
58 __asm__
volatile(
"rsr.intenable3 %0" :
"=r"(val));
60 __asm__
volatile(
"wsr.intenable3 %0; rsync" : :
"r"(val));
70static inline void z_xt_ints_off(
unsigned int mask)
74 __asm__
volatile(
"rsr.intenable %0" :
"=r"(val));
76 __asm__
volatile(
"wsr.intenable %0; rsync" : :
"r"(val));
78#if XCHAL_NUM_INTERRUPTS > 32
79static inline void z_xt_ints1_off(
unsigned int mask)
83 __asm__
volatile(
"rsr.intenable1 %0" :
"=r"(val));
85 __asm__
volatile(
"wsr.intenable1 %0; rsync" : :
"r"(val));
88#if XCHAL_NUM_INTERRUPTS > 64
89static inline void z_xt_ints2_off(
unsigned int mask)
93 __asm__
volatile(
"rsr.intenable2 %0" :
"=r"(val));
95 __asm__
volatile(
"wsr.intenable2 %0; rsync" : :
"r"(val));
98#if XCHAL_NUM_INTERRUPTS > 96
99static inline void z_xt_ints3_off(
unsigned int mask)
103 __asm__
volatile(
"rsr.intenable3 %0" :
"=r"(val));
105 __asm__
volatile(
"wsr.intenable3 %0; rsync" : :
"r"(val));
113static inline void z_xt_set_intset(
unsigned int arg)
115#if XCHAL_HAVE_INTERRUPTS
116 __asm__
volatile(
"wsr.intset %0; rsync" : :
"r"(arg));
121#if XCHAL_NUM_INTERRUPTS > 32
122static inline void z_xt_set_intset1(
unsigned int arg)
124 __asm__
volatile(
"wsr.intset1 %0; rsync" : :
"r"(arg));
127#if XCHAL_NUM_INTERRUPTS > 64
128static inline void z_xt_set_intset2(
unsigned int arg)
130 __asm__
volatile(
"wsr.intset2 %0; rsync" : :
"r"(arg));
133#if XCHAL_NUM_INTERRUPTS > 96
134static inline void z_xt_set_intset3(
unsigned int arg)
136 __asm__
volatile(
"wsr.intset3 %0; rsync" : :
"r"(arg));
145#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
150#ifdef CONFIG_2ND_LEVEL_INTERRUPTS
151#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
152#define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\
153 (CONFIG_NUM_2ND_LEVEL_AGGREGATORS +\
154 CONFIG_NUM_3RD_LEVEL_AGGREGATORS) *\
155 CONFIG_MAX_IRQ_PER_AGGREGATOR)
157#define CONFIG_NUM_IRQS (XCHAL_NUM_INTERRUPTS +\
158 CONFIG_NUM_2ND_LEVEL_AGGREGATORS *\
159 CONFIG_MAX_IRQ_PER_AGGREGATOR)
162#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
165void z_soc_irq_init(
void);
166void z_soc_irq_enable(
unsigned int irq);
167void z_soc_irq_disable(
unsigned int irq);
168int z_soc_irq_is_enabled(
unsigned int irq);
170#define arch_irq_enable(irq) z_soc_irq_enable(irq)
171#define arch_irq_disable(irq) z_soc_irq_disable(irq)
173#define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq)
175#ifdef CONFIG_DYNAMIC_INTERRUPTS
176extern int z_soc_irq_connect_dynamic(
unsigned int irq,
unsigned int priority,
177 void (*routine)(
const void *parameter),
183#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
185#define arch_irq_enable(irq) xtensa_irq_enable(irq)
186#define arch_irq_disable(irq) xtensa_irq_disable(irq)
188#define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq)
199#if XCHAL_NUM_INTERRUPTS > 32
202 z_xt_ints_on(1 << irq);
205 z_xt_ints1_on(1 << irq);
207#if XCHAL_NUM_INTERRUPTS > 64
209 z_xt_ints2_on(1 << irq);
212#if XCHAL_NUM_INTERRUPTS > 96
214 z_xt_ints3_on(1 << irq);
221 z_xt_ints_on(1 << irq);
232#if XCHAL_NUM_INTERRUPTS > 32
235 z_xt_ints_off(1 << irq);
238 z_xt_ints1_off(1 << irq);
240#if XCHAL_NUM_INTERRUPTS > 64
242 z_xt_ints2_off(1 << irq);
245#if XCHAL_NUM_INTERRUPTS > 96
247 z_xt_ints3_off(1 << irq);
254 z_xt_ints_off(1 << irq);
263 __asm__
volatile(
"rsil %0, %1"
264 :
"=r"(key) :
"i"(XCHAL_EXCM_LEVEL) :
"memory");
271 __asm__
volatile(
"wsr.ps %0; rsync"
272 ::
"r"(key) :
"memory");
278 return (key & 0xf) == 0;
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Disable all interrupts on the local CPU.
Definition irq.h:168
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
Definition irq.h:176
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
Definition irq.h:181
static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
Disable interrupt on Xtensa core.
Definition irq.h:230
static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
Enable interrupt on Xtensa core.
Definition irq.h:197
int xtensa_irq_is_enabled(unsigned int irq)
Query if an interrupt is enabled on Xtensa core.
Public interface for configuring interrupts.
flags
Definition parser.h:97
__UINT32_TYPE__ uint32_t
Definition stdint.h:90