8#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
9#define ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
16#define MPU_IR_REGION_Msk (0xFFU)
18#define MPU_RBAR_BASE_Pos 6U
19#define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
20#define MPU_RBAR_SH_Pos 4U
21#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
22#define MPU_RBAR_AP_Pos 2U
23#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
25#define MPU_RBAR_XN_Pos 1U
26#define MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos)
29#define MPU_RLAR_LIMIT_Pos 6U
30#define MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
31#define MPU_RLAR_AttrIndx_Pos 1U
32#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
33#define MPU_RLAR_EN_Msk (0x1UL)
36#define NOT_EXEC MPU_RBAR_XN_Msk
41#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
44#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
47#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
50#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
53#define NON_SHAREABLE 0x0U
54#define NON_SHAREABLE_Msk \
55 ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
56#define OUTER_SHAREABLE 0x2U
57#define OUTER_SHAREABLE_Msk \
58 ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
59#define INNER_SHAREABLE 0x3U
60#define INNER_SHAREABLE_Msk \
61 ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
83#define DEVICE_nGnRnE 0x0U
84#define DEVICE_nGnRE 0x4U
85#define DEVICE_nGRE 0x8U
86#define DEVICE_GRE 0xCU
89#define R_NON_W_NON 0x0U
90#define R_NON_W_ALLOC 0x1U
91#define R_ALLOC_W_NON 0x2U
92#define R_ALLOC_W_ALLOC 0x3U
95#define NORMAL_O_WT_NT 0x80U
96#define NORMAL_O_WB_NT 0xC0U
97#define NORMAL_O_NON_C 0x40U
99#define NORMAL_I_WT_NT 0x08U
100#define NORMAL_I_WB_NT 0x0CU
101#define NORMAL_I_NON_C 0x04U
104#define MPU_MAIR_INDEX_DEVICE 0U
105#define MPU_MAIR_ATTR_DEVICE (DEVICE_nGnRnE)
107#define MPU_MAIR_INDEX_FLASH 1U
108#define MPU_MAIR_ATTR_FLASH \
109 ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | \
110 (NORMAL_I_WT_NT | R_ALLOC_W_NON))
112#define MPU_MAIR_INDEX_SRAM 2U
113#define MPU_MAIR_ATTR_SRAM \
114 ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | \
115 (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
117#define MPU_MAIR_INDEX_SRAM_NOCACHE 3U
118#define MPU_MAIR_ATTR_SRAM_NOCACHE \
119 ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | \
120 (NORMAL_I_NON_C | R_NON_W_NON))
122#define MPU_MAIR_ATTRS \
123 ((MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)) | \
124 (MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) | \
125 (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \
126 (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)))
135#define REGION_IO_ATTR \
138 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
140 .mair_idx = MPU_MAIR_INDEX_DEVICE, \
143#define REGION_RAM_ATTR \
146 .rbar = NOT_EXEC | P_RW_U_NA_Msk | OUTER_SHAREABLE_Msk, \
148 .mair_idx = MPU_MAIR_INDEX_SRAM, \
151#define REGION_RAM_NOCACHE_ATTR \
154 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
156 .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, \
159#define REGION_RAM_TEXT_ATTR \
162 .rbar = P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, \
164 .mair_idx = MPU_MAIR_INDEX_SRAM, \
167#define REGION_RAM_RO_ATTR \
170 .rbar = NOT_EXEC | P_RO_U_RO_Msk | INNER_SHAREABLE_Msk, \
172 .mair_idx = MPU_MAIR_INDEX_SRAM, \
175#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
178#define REGION_FLASH_ATTR \
180 .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, \
182 .mair_idx = MPU_MAIR_INDEX_FLASH, \
185#define REGION_FLASH_ATTR \
187 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, \
189 .mair_idx = MPU_MAIR_INDEX_FLASH, \
222#define MPU_REGION_ENTRY(_name, _base, _limit, _attr) \
230#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \
231 {(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
232#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \
233 {(P_RW_U_NA_Msk), MPU_MAIR_INDEX_SRAM})
234#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \
235 {(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
236#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \
237 {(P_RO_U_NA_Msk), MPU_MAIR_INDEX_SRAM})
256#define ARM64_MPU_MAX_DYNAMIC_REGIONS \
258 (CONFIG_MAX_DOMAIN_PARTITIONS + 2) + \
259 (IS_ENABLED(CONFIG_ARM64_STACK_PROTECTION) ? 2 : 0) + \
260 (IS_ENABLED(CONFIG_USERSPACE) ? 2 : 0)
const struct arm_mpu_config mpu_config
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
uint32_t num_regions
Definition arm_mpu.h:44
const struct arm_mpu_region * mpu_regions
Definition arm_mpu.h:46
Definition arm_mpu_v7m.h:152
uint8_t rbar
Definition arm_mpu_v8.h:309
uint8_t mair_idx
Definition arm_mpu_v8.h:311
const char * name
Definition arm_mpu.h:32
uint64_t limit
Definition arm_mpu.h:207
uint64_t base
Definition arm_mpu.h:205
arm_mpu_region_attr_t attr
Definition arm_mpu.h:38
int index
Definition arm_mpu.h:252
struct arm_mpu_region region_conf
Definition arm_mpu.h:253
Definition arm_mpu_v7m.h:160